From patchwork Mon Aug 14 10:16:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 13352675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02FBCC04A94 for ; Mon, 14 Aug 2023 10:16:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=gMPBLO+hM+xprNq8F+XPgNQGGlQVr43NNJ91gZKnzPE=; b=3usLhBAmGr0hE8 8q/PF3UgXpZ6SDa7N5VWp3xdv6TGHDvJF/omV0+bZxObblLFdr8eKCY9us0dke6chjvhWiK1B8YFJ MXRV9/wVluw+U6MgiLzVUyioNIg7Y/PKJqDyFq95byVhdTgHGjmE9MZoVZjUbjfdbM2efpdsTAe5l dWJ9EcltEftEXTPsn3aRLHGYlM4UhXoMzETW/jvqg1mOMUozdzugzzKSAGW536uzs2ybexT4nc5bt kCwX63q5kV8wVfbesk0X2LEXDLtOqt0/QHZZzdjzTuZB2YeJurLW9XyJi54ZBqkobJyP6FZXrWkmG ik042xJAJQ2uv+t1F1xg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qVUcu-00Ghre-1Q; Mon, 14 Aug 2023 10:16:44 +0000 Received: from fd01.gateway.ufhost.com ([61.152.239.71]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qVUcp-00Gho8-1m for linux-riscv@lists.infradead.org; Mon, 14 Aug 2023 10:16:42 +0000 Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 9F0A081EA; Mon, 14 Aug 2023 18:16:04 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 14 Aug 2023 18:16:04 +0800 Received: from localhost.localdomain (183.27.98.20) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 14 Aug 2023 18:16:03 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Xingyu Wu , Samin Guo , , Conor Dooley Subject: [PATCH v4 0/3] Add timer driver for StarFive JH7110 RISC-V SoC Date: Mon, 14 Aug 2023 18:16:00 +0800 Message-ID: <20230814101603.166951-1-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [183.27.98.20] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230814_031639_978267_BCA0E99D X-CRM114-Status: GOOD ( 13.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch serises are to add timer driver for the StarFive JH7110 RISC-V SoC. The first patch adds documentation to describe device tree bindings. The subsequent patch adds timer driver and support JH7110 SoC. The last patch adds device node about timer in JH7110 dts. This timer has four free-running 32 bit counters and runs in 24MHz clock on StarFive JH7110 SoC. And each channel(counter) triggers an interrupt when timeout. They support one-shot mode and continuous-run mode. Changes since v3: - Rebased on 6.5-rc6 - Dropped the useless enum names like 'JH7110_TIMER_CH_0'. - Dropped the platform data about JH7110 and used the register offsets directly. - Drroped the useless functions of clk_disable_unprepare(). v3: https://lore.kernel.org/all/20230627055313.252519-1-xingyu.wu@starfivetech.com/ Changes since v2: - Rebased on 6.4-rc7. - Merged the header file into the c file. - Renamed the functions from 'starfive_' to 'jh7110_' - Used function 'clocksource_register_hz' instead of 'clocksource_mmio_init'. v2: https://lore.kernel.org/all/20230320135433.144832-1-xingyu.wu@starfivetech.com/ Changes since v1: - Added description about timer and modified properties' description in dt-bindings. - Dropped the 'interrupt-names' and 'clock-frequency' in dt-bindings. - Renamed the functions and added 'starfive_' - Modified that the driver probe by platform bus. v1: https://lore.kernel.org/all/20221223094801.181315-1-xingyu.wu@starfivetech.com/ Xingyu Wu (3): dt-bindings: timer: Add timer for StarFive JH7110 SoC clocksource: Add JH7110 timer driver riscv: dts: jh7110: starfive: Add timer node .../bindings/timer/starfive,jh7110-timer.yaml | 96 ++++ MAINTAINERS | 7 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-jh7110.c | 415 ++++++++++++++++++ 6 files changed, 550 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml create mode 100644 drivers/clocksource/timer-jh7110.c