[0/4] Support Andes PMU extension

Message

Yu-Chien Peter Lin Sept. 7, 2023, 2:16 a.m. UTC

This patch series introduces the Andes PMU errata, which
adds support for perf sampling and mode filtering with
the Andes PMU extension. 

The custom PMU extension serves the same purpose as Sscofpmf.
Its non-standard local interrupt is assigned to bit 18 in the
custom S-mode local interrupt pending CSR (slip), while the
interrupt cause is (256 + 18).

This series is dependent on the series from Prabhakar,
- https://patchwork.kernel.org/project/linux-riscv/cover/[e-mail]/

The feature needs the PMU device callbacks in OpenSBI.
The OpenSBI and Linux patches can be found on Andes Technology GitHub
- https://github.com/andestech/opensbi/commits/andes-pmu-support
- https://github.com/andestech/linux/commits/andes-pmu-support

The PMU device tree node of AX45MP:
- https://github.com/andestech/opensbi/blob/andes-pmu-support/docs/pmu_support.md#example-3

Tested hardware:
- ASUS  Tinker-V (RZ/Five, AX45MP single core)
- Andes AE350    (AX45MP quad core)

Locus Wei-Han Chen (1):
  riscv: andes: Support symbolic FW and HW raw events

Yu Chien Peter Lin (3):
  riscv: errata: Rename defines for Andes
  irqchip/riscv-intc: Support large non-standard hwirq number
  riscv: errata: Add Andes PMU errata

 arch/riscv/Kconfig.errata                     |  13 ++
 arch/riscv/errata/andes/errata.c              |  55 +++++++-
 arch/riscv/include/asm/errata_list.h          |  45 ++++++-
 arch/riscv/include/asm/vendorid_list.h        |   2 +-
 arch/riscv/kernel/alternative.c               |   2 +-
 drivers/irqchip/irq-riscv-intc.c              |  10 +-
 drivers/perf/riscv_pmu_sbi.c                  |  20 ++-
 .../arch/riscv/andes/ax45/firmware.json       |  68 ++++++++++
 .../arch/riscv/andes/ax45/instructions.json   | 127 ++++++++++++++++++
 .../arch/riscv/andes/ax45/memory.json         |  57 ++++++++
 .../arch/riscv/andes/ax45/microarch.json      |  77 +++++++++++
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |   1 +
 12 files changed, 453 insertions(+), 24 deletions(-)
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json