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([2a01:e0a:999:a3a0:b380:32be:257:5381]) by smtp.gmail.com with ESMTPSA id r9-20020a056000014900b003232f167df5sm14316589wrx.108.2023.10.26.07.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 07:31:26 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Himanshu Chauhan , Xu Lu Subject: [RFC PATCH 0/3] riscv: add support for SBI Supervisor Software Events Date: Thu, 26 Oct 2023 16:31:19 +0200 Message-ID: <20231026143122.279437-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_073130_591538_D1311C03 X-CRM114-Status: GOOD ( 20.44 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The SBI Supervisor Software Events (SSE) extensions provides a mechanism to inject software events from an SBI implementation to supervisor software such that it preempts all other supervisor level traps and interrupts [1]. Various events are defined and can be send asynchronously to supervisor software (RAS, PMU, DEBUG, Asynchronous page fault) from SBI as well as platform specific events. Events can be either local (per-hart) or global. Events can be nested on top of each other based on priority and can interrupt the kernel at any time. First patch adds the SSE definitions. Second one adds support for SSE itself. Implementation is split between arch specific code and generic part (similarly to what is done for ARM SDEI). Finally, the last patch add support fro SSE event in the SBI PMU driver. If the SSE event is available from the SBI then, it will be used instead of the normal interrupt. Amongst the specific points that needs to be handle is the interruption at any point of the kernel execution and more specifically during exception handling. Due to the fact that the exception entry implementation uses the SCRATCH CSR as both the current task struct and as the temporary register to switch the stack and save register, it is difficult to reliably get the current task struct if we get interrupted at this specific moment. A fixup-like mechanism allows to mark the location of the current task struct depending on the entry level (user/kernel) and the location. This is then used in the SSE assembly to determine where is located the current task_struct. Contrary to pseudo NMI [2], SSE does not modifies the way interrupts are handled and does not adds any overhead to existing code. Moreover, it provides "true" NMI-like interrupts which can interrupt the kernel at any time (even in exception handling). This is particularly crucial for RAS errors which needs to be handled as fast as possible to avoid any fault propagation. Additionally, SSE event handling is faster that the standard IRQ handling path with almost half executed instruction (700 vs 1590). Some complementary tests/perf measurements will be done. For testing purpose, one can use the provided SBI implementation at [3]. This series also needs patch [4] to fix a bug in the PMU driver. Link: https://lists.riscv.org/g/tech-prs/message/515 [1] Link: https://lore.kernel.org/lkml/20231023082911.23242-10-luxu.kernel@bytedance.com/T/ [2] Link: https://github.com/rivosinc/opensbi/tree/dev/cleger/sse [3] Link: https://lore.kernel.org/linux-arm-kernel/20231026084010.11888-1-alexghiti@rivosinc.com/ [4] --- Clément Léger (3): riscv: add SBI SSE extension definitions riscv: add support for SBI Supervisor Software Events extension perf: RISC-V: add support for SSE event arch/riscv/include/asm/asm-prototypes.h | 5 + arch/riscv/include/asm/sbi.h | 40 ++ arch/riscv/include/asm/sse.h | 94 +++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 17 + arch/riscv/kernel/entry.S | 156 ++++++++ arch/riscv/kernel/sbi.c | 4 + arch/riscv/kernel/sse.c | 97 +++++ arch/riscv/kernel/stacktrace.c | 13 + arch/riscv/kernel/vmlinux.lds.S | 6 + drivers/firmware/Kconfig | 10 + drivers/firmware/Makefile | 1 + drivers/firmware/riscv_sse.c | 496 ++++++++++++++++++++++++ drivers/perf/riscv_pmu_sbi.c | 51 ++- include/linux/riscv_sse.h | 56 +++ 15 files changed, 1038 insertions(+), 9 deletions(-) create mode 100644 arch/riscv/include/asm/sse.h create mode 100644 arch/riscv/kernel/sse.c create mode 100644 drivers/firmware/riscv_sse.c create mode 100644 include/linux/riscv_sse.h