| Message ID | 20231126232746.264302-1-emil.renner.berthing@canonical.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add JH7100 errata and update device tree | expand |
On Mon, Nov 27, 2023 at 12:27:38AM +0100, Emil Renner Berthing wrote: > Now that the driver for the SiFive cache controller supports manual > flushing as non-standard cache operations[1] we can add an errata option > for the StarFive JH7100 SoC and update the device tree with the cache > controller, dedicated DMA pool and add MMC nodes for the SD-card and > wifi. > > This series needs the following commit in [1] to work properly: > > 0d5701dc9cd6 ("soc: sifive: ccache: Add StarFive JH7100 support") > > [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-soc-for-next This stuff all seems fine to me. I'd like Palmer to take the first patch, or I suppose I could take it alongside the cache driver changes with an Ack. Cheers, Conor.
Conor Dooley wrote: > On Mon, Nov 27, 2023 at 12:27:38AM +0100, Emil Renner Berthing wrote: > > Now that the driver for the SiFive cache controller supports manual > > flushing as non-standard cache operations[1] we can add an errata option > > for the StarFive JH7100 SoC and update the device tree with the cache > > controller, dedicated DMA pool and add MMC nodes for the SD-card and > > wifi. > > > > This series needs the following commit in [1] to work properly: > > > > 0d5701dc9cd6 ("soc: sifive: ccache: Add StarFive JH7100 support") > > > > [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-soc-for-next > > This stuff all seems fine to me. I'd like Palmer to take the first > patch, or I suppose I could take it alongside the cache driver changes > with an Ack. Thanks, makes sense. In addition to the missing Signed-off-by I also forgot to update the commit message for patch 4/8, so let me send a v2. /Emil
Now that the driver for the SiFive cache controller supports manual flushing as non-standard cache operations[1] we can add an errata option for the StarFive JH7100 SoC and update the device tree with the cache controller, dedicated DMA pool and add MMC nodes for the SD-card and wifi. This series needs the following commit in [1] to work properly: 0d5701dc9cd6 ("soc: sifive: ccache: Add StarFive JH7100 support") [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-soc-for-next Emil Renner Berthing (7): riscv: errata: Add StarFive JH7100 errata riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs riscv: dts: starfive: Add JH7100 cache controller riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards riscv: dts: starfive: Add JH7100 MMC nodes riscv: dts: starfive: Enable SD-card on JH7100 boards riscv: dts: starfive: Enable SDIO wifi on JH7100 boards Geert Uytterhoeven (1): riscv: dts: starfive: Group tuples in interrupt properties arch/riscv/Kconfig.errata | 17 +++ .../boot/dts/starfive/jh7100-common.dtsi | 131 ++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 48 ++++++- 3 files changed, 192 insertions(+), 4 deletions(-)