| Message ID | 20231202140323.315-1-jszhang@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: enable lockless lockref implementation | expand |
On Sat, Dec 02, 2023 at 10:03:21PM +0800, Jisheng Zhang wrote: > This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the > cmpxchg-based lockless lockref implementation for riscv. Then, > implement arch_cmpxchg64_{relaxed|acquire|release}. > > After patch1: > Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. > On JH7110 platform, I see 12.0% improvement. > > After patch2: > on both TH1520 and JH7110 platforms, I didn't see obvious > performance improvement with Linus' test case [1]. IMHO, this may > be related with the fence and lr.d/sc.d hw implementations. In theory, > lr/sc without fence could give performance improvement over lr/sc plus > fence, so add the code here to leave performance improvement room on > newer HW platforms. > > Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] Hi Palmer, this series is also missed, let me know if there's something need to be done. Thanks > > Since v1: > - only select ARCH_USE_CMPXCHG_LOCKREF if 64BIT > > Jisheng Zhang (2): > riscv: select ARCH_USE_CMPXCHG_LOCKREF > riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} > > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++ > 2 files changed, 19 insertions(+) > > -- > 2.42.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Sat, Dec 02, 2023 at 10:03:21PM +0800, Jisheng Zhang wrote: > This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the > cmpxchg-based lockless lockref implementation for riscv. Then, > implement arch_cmpxchg64_{relaxed|acquire|release}. > > After patch1: > Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. > On JH7110 platform, I see 12.0% improvement. > > After patch2: > on both TH1520 and JH7110 platforms, I didn't see obvious > performance improvement with Linus' test case [1]. IMHO, this may > be related with the fence and lr.d/sc.d hw implementations. In theory, > lr/sc without fence could give performance improvement over lr/sc plus > fence, so add the code here to leave performance improvement room on > newer HW platforms. > > Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] > > Since v1: > - only select ARCH_USE_CMPXCHG_LOCKREF if 64BIT > > Jisheng Zhang (2): > riscv: select ARCH_USE_CMPXCHG_LOCKREF > riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} For the series, Reviewed-by: Andrea Parri <parri.andrea@gmail.com> # code audit, QEMU tests Andrea
This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the cmpxchg-based lockless lockref implementation for riscv. Then, implement arch_cmpxchg64_{relaxed|acquire|release}. After patch1: Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. On JH7110 platform, I see 12.0% improvement. After patch2: on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] Since v1: - only select ARCH_USE_CMPXCHG_LOCKREF if 64BIT Jisheng Zhang (2): riscv: select ARCH_USE_CMPXCHG_LOCKREF riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} arch/riscv/Kconfig | 1 + arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+)