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([2a01:e0a:999:a3a0:c564:f167:d072:5672]) by smtp.gmail.com with ESMTPSA id m27-20020a05600c3b1b00b0040b38292253sm22433137wms.30.2023.12.13.03.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 03:33:11 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn Subject: [PATCH 0/9] riscv: hwprobe: add Zicond, Zam, Zacas and Ztso support Date: Wed, 13 Dec 2023 12:32:56 +0100 Message-ID: <20231213113308.133176-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231213_033320_918739_AAF826C3 X-CRM114-Status: UNSURE ( 7.52 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series add support for a few more extensions that are present in the RVA22U64/RVA23U64 (either mandatory or optional) and that are useful for userspace: - Zicond - Zam - Zacas - Ztso Series currently based on riscv/for-next. Clément Léger (9): riscv: add ISA extension parsing for Ztso riscv: hwprobe: export Ztso ISA extension dt-bindings: riscv: add Zam ISA extension description riscv: add ISA extension parsing for Zam riscv: hwprobe: export Zam ISA extension dt-bindings: riscv: add Zacas ISA extension description riscv: add ISA extension parsing for Zacas riscv: hwprobe: export Zacas ISA extension riscv: hwprobe: export Zicond extension Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++ .../devicetree/bindings/riscv/extensions.yaml | 11 +++++++++++ arch/riscv/include/asm/hwcap.h | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 3 +++ arch/riscv/kernel/sys_riscv.c | 4 ++++ 6 files changed, 41 insertions(+)