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[v6,00/10] riscv: support kernel-mode Vector

Message ID 20231220075412.24084-1-andy.chiu@sifive.com (mailing list archive)
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Series riscv: support kernel-mode Vector | expand

Message

Andy Chiu Dec. 20, 2023, 7:54 a.m. UTC
This series provides support for running Vector code in kernel mode.
Along with the suport, we add some Vector optimized routines. And
provide a simple threshold to decide when to run the vectorized
functions.

I am adding back preemptible Vector as they are ready for review now.
Having them together makes it easier to be reviewed and tested.
Meanwhile, as they are appended at the end, this series can be merged
incrementally if we feel any part of {1~4, 5~6, 7~10} is mature enough.

This patch is tested on a QEMU with V and verified that booting, normal
userspace operations all work as usual with thresholds set to 0. Also,
we test by launching multiple kernel threads which continuously executes
and verifies Vector operations in the background.

v5 of this series can be found at [1]

Link: https://lore.kernel.org/all/20231214155721.1753-1-andy.chiu@sifive.com/

Patch summary (on current order, 7~10 are compared with v3):
 - Updated patches: 1, 5, 6, 10
 - New patch: 8, 9
 - Unchanged patch: 2, 3, 4, 7
 - Deleted patch: none

Changelog v6:
 - Provide a more robust check on the use of non-preemptible Vector.
 - Add Kconfigs to set threshold value at compile time. (Charlie)
 - Add a patch to utilize kmem_cache_* for V context allocations.
 - Re-write and add preemptible Vector.

Changelog v5:
 - Rebase on top of riscv for-next (6.7-rc1)
Changelog v4:
 - Use kernel_v_flags and helpers to track vector context.
 - Prevent softirq from nesting V context for non-preempt V
 - Add user copy and mem* routines

Changelog v3:
 - Rebase on top of riscv for-next (6.6-rc1)
 - Fix a build issue (Conor)
 - Guard vstate_save, vstate_restore with {get,put}_cpu_vector_context.
 - Save V context after disabling preemption. (Guo)
 - Remove irqs_disabled() check from may_use_simd(). (Björn)
 - Comment about nesting V context.

Changelog v2:
 - fix build issues
 - Follow arm's way of starting kernel-mode simd code:
   - add include/asm/simd.h and rename may_use_vector() ->
     may_use_simd()
   - return void in kernel_vector_begin(), and BUG_ON if may_use_simd()
     fails
 - Change naming scheme for functions/macros (Conor):
   - remove KMV
   - 's/rvv/vector/'
   - 's/RISCV_ISA_V_PREEMPTIVE_KMV/RISCV_ISA_V_PREEMPTIVE/'
   - 's/TIF_RISCV_V_KMV/TIF_RISCV_V_KERNEL_MODE/'

Andy Chiu (8):
  riscv: vector: make Vector always available for softirq context
  riscv: sched: defer restoring Vector context for user
  riscv: lib: vectorize copy_to_user/copy_from_user
  riscv: lib: add vectorized mem* routines
  riscv: vector: do not pass task_struct into
    riscv_v_vstate_{save,restore}()
  riscv: vector: use a mask to write vstate_ctrl
  riscv: vector: use kmem_cache to manage vector context
  riscv: vector: allow kernel-mode Vector with preemption

Greentime Hu (2):
  riscv: Add support for kernel mode vector
  riscv: Add vector extension XOR implementation

 arch/riscv/Kconfig                     |  46 ++++++
 arch/riscv/include/asm/entry-common.h  |  17 ++
 arch/riscv/include/asm/processor.h     |  39 ++++-
 arch/riscv/include/asm/simd.h          |  62 ++++++++
 arch/riscv/include/asm/thread_info.h   |   2 +
 arch/riscv/include/asm/vector.h        | 103 ++++++++++--
 arch/riscv/include/asm/xor.h           |  82 ++++++++++
 arch/riscv/kernel/Makefile             |   1 +
 arch/riscv/kernel/entry.S              |   8 +
 arch/riscv/kernel/kernel_mode_vector.c | 212 +++++++++++++++++++++++++
 arch/riscv/kernel/process.c            |  14 +-
 arch/riscv/kernel/ptrace.c             |   7 +-
 arch/riscv/kernel/signal.c             |   7 +-
 arch/riscv/kernel/vector.c             |  50 +++++-
 arch/riscv/lib/Makefile                |   6 +
 arch/riscv/lib/memcpy_vector.S         |  29 ++++
 arch/riscv/lib/memmove_vector.S        |  49 ++++++
 arch/riscv/lib/memset_vector.S         |  33 ++++
 arch/riscv/lib/riscv_v_helpers.c       |  60 +++++++
 arch/riscv/lib/uaccess.S               |  10 ++
 arch/riscv/lib/uaccess_vector.S        |  50 ++++++
 arch/riscv/lib/xor.S                   |  81 ++++++++++
 22 files changed, 942 insertions(+), 26 deletions(-)
 create mode 100644 arch/riscv/include/asm/simd.h
 create mode 100644 arch/riscv/include/asm/xor.h
 create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
 create mode 100644 arch/riscv/lib/memcpy_vector.S
 create mode 100644 arch/riscv/lib/memmove_vector.S
 create mode 100644 arch/riscv/lib/memset_vector.S
 create mode 100644 arch/riscv/lib/riscv_v_helpers.c
 create mode 100644 arch/riscv/lib/uaccess_vector.S
 create mode 100644 arch/riscv/lib/xor.S