From patchwork Mon Dec 25 10:32:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13504577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65005C47072 for ; Mon, 25 Dec 2023 10:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=ZCUdf7UQ0zmDI7cECjzoDhuJhCKoCvkqLL/j3FWCEFQ=; b=bb5z6t0VTlXuky Tg4Y5r4btnBAFxutw5Y4Co0Cjeyw9XyLUtW9/PYmBAsfAnKhjEas1iHvFwMxtmuR1NlzWSlCNVIJ2 U7o++prKRJfB3ehKnK4vK2IOxwRxzIhy3Utc8VRbMsXHJ75mzrSGO1CjYE0e51IW42GPreRLPMybX hP/svksL+9OA/x094uAN36uT4Dj+zo/uhz1V5tmqnRvTTm8xmYSG9Ba1Shb35T5q6oq5JbPB31cJD F4YIGUmrJ8siSX/LGDiYdhZF95Y2iQZbMiy8jKCwybgKrrBc5WMqiybBz3Tcro2cLNJNr1oOYwMBd no+7PUT88P4heAOZ1kaw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rHiIh-00AYD9-39; Mon, 25 Dec 2023 10:35:11 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rHiIU-00AY64-24; Mon, 25 Dec 2023 10:35:02 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAXCXq093056; Mon, 25 Dec 2023 18:33:12 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:33:12 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 00/16] Support Andes PMU extension Date: Mon, 25 Dec 2023 18:32:52 +0800 Message-ID: <20231225103308.1557548-1-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BPAXCXq093056 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231225_023459_226512_803C31A2 X-CRM114-Status: GOOD ( 10.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi All, This patch series introduces the Andes PMU extension, which serves the same purpose as Sscofpmf. To use FDT-based probing for hardware support of the PMU extensions, we first convert T-Head's PMU to CPU feature alternative, then add Andes PMU alternatives. Its non-standard local interrupt is assigned to bit 18 in the custom S-mode local interrupt enable/pending registers (slie/slip), while the interrupt cause is (256 + 18). Mainline OpenSBI has supported Andes PMU extension: - https://github.com/riscv-software-src/opensbi/tree/master Linux patches (based on v6.7-rc7) can be found on Andes Technology GitHub - https://github.com/andestech/linux/commits/andes-pmu-support-v6 The PMU device tree node used on AX45MP: - https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3 Locus Wei-Han Chen (1): riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin (15): riscv: errata: Rename defines for Andes irqchip/riscv-intc: Allow large non-standard interrupt number irqchip/riscv-intc: Introduce Andes hart-level interrupt controller dt-bindings: riscv: Add Andes interrupt controller compatible string riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC perf: RISC-V: Eliminate redundant interrupt enable/disable operations RISC-V: Move T-Head PMU to CPU feature alternative framework perf: RISC-V: Introduce Andes PMU for perf event sampling dt-bindings: riscv: Add T-Head PMU extension description dt-bindings: riscv: Add Andes PMU extension description riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s riscv: dts: sophgo: Add T-Head PMU extension for cv1800b riscv: dts: sophgo: Add T-Head PMU extension for sg2042 riscv: dts: thead: Add T-Head PMU extension for th1520 riscv: dts: renesas: Add Andes PMU extension for r9a07g043f .../devicetree/bindings/riscv/cpus.yaml | 6 +- .../devicetree/bindings/riscv/extensions.yaml | 13 ++ arch/riscv/Kconfig.errata | 13 -- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 +++++++++--------- arch/riscv/boot/dts/thead/th1520.dtsi | 8 +- arch/riscv/errata/andes/errata.c | 10 +- arch/riscv/errata/thead/errata.c | 19 --- arch/riscv/include/asm/errata_list.h | 19 +-- arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/alternative.c | 2 +- arch/riscv/kernel/cpufeature.c | 2 + drivers/irqchip/irq-riscv-intc.c | 89 ++++++++++-- drivers/perf/Kconfig | 27 ++++ drivers/perf/riscv_pmu_sbi.c | 47 +++++-- include/linux/soc/andes/irq.h | 18 +++ .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 +++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 24 files changed, 592 insertions(+), 151 deletions(-) create mode 100644 include/linux/soc/andes/irq.h create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json