[-fixes,v2,0/4] riscv: cbo.zero fixes

Message

Samuel Holland Feb. 13, 2024, 3:37 a.m. UTC

This series fixes a couple issues related to using the cbo.zero
instruction in userspace. The first patches fixes a bug where the wrong
enable bit gets set if the kernel is running in M-mode. The remaining
patches fix a bug where the enable bit gets reset to its default value
after a nonretentive idle state. I have hardware which reproduces this:

Before this series (or without ss1p12 in the devicetree):
  $ tools/testing/selftests/riscv/hwprobe/cbo
  TAP version 13
  1..3
  ok 1 Zicboz block size
  # Zicboz block size: 64
  Illegal instruction

After applying this series:
  $ tools/testing/selftests/riscv/hwprobe/cbo
  TAP version 13
  1..3
  ok 1 Zicboz block size
  # Zicboz block size: 64
  ok 2 cbo.zero
  ok 3 cbo.zero check
  # Totals: pass:3 fail:0 xfail:0 xpass:0 skip:0 error:0

Changes in v2:
 - Add patches to allow parsing the privileged ISA version from the DT
 - Check for privileged ISA v1.12 instead of the specific CSR
 - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s

Samuel Holland (4):
  riscv: Fix enabling cbo.zero when running in M-mode
  dt-bindings: riscv: Add ratified privileged ISA versions
  riscv: Add ISA extension parsing for Sm and Ss
  riscv: Save/restore envcfg CSR during CPU suspend

 .../devicetree/bindings/riscv/extensions.yaml | 20 +++++++++
 arch/riscv/include/asm/cpufeature.h           |  1 +
 arch/riscv/include/asm/csr.h                  |  2 +
 arch/riscv/include/asm/hwcap.h                |  8 ++++
 arch/riscv/include/asm/suspend.h              |  1 +
 arch/riscv/kernel/cpu.c                       |  5 +++
 arch/riscv/kernel/cpufeature.c                | 44 ++++++++++++++++---
 arch/riscv/kernel/suspend.c                   |  4 ++
 8 files changed, 79 insertions(+), 6 deletions(-)