[v2,0/7] Support Zve32[xf] and Zve64[xfd] Vector subextensions

Message

Andy Chiu March 14, 2024, 2:25 p.m. UTC

The series composes of two parts. The first part provides a quick fix for
the issue on a recent thread[1]. The issue happens when a platform has
ununified vector register length across multiple cores. Specifically,
patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
vlenb is observed by the system. Patch 2 fixes the issue by failing the
boot process of a secondary core if vlenb mismatches.

The second part of the series provide a finer grain view of the Vector
extension. Patch 3 give the obsolete ISA parser the ability to expand
ISA extensions for sigle letter extensions. Patch 3, 4 introduces Zve32x,
Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe. Patch 5
updates all callsites such that Vector subextensions are maximumly
supported by the kernel.

Two parts of the series are sent together to ease the effort of picking
dependency patches. The first part can be merged independent of the
second one if necessary.

The series is tested on a QEMU and verified that booting, Vector
programs context-switch, signal, ptrace, prctl(sysctl knob) interfaces
works when we only report partial V from the ISA.

This patch should be able to apply on risc-v for-next branch on top of
the commit 886516fae2b7 ("RISC-V: fix check for zvkb with tip-of-tree clang")

[1]: https://lore.kernel.org/all/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/T/#u

v1 of this series can be found at: https://lore.kernel.org/all/[e-mail]/

Changelog v2:
 - Update comments and commit messages (1, 2, 7)
 - Refine isa_exts[] lists for zve extensions (4)
 - Add a patch for dt-binding (5)
 - Make ZVE* extensions depend on has_vector(ZVE32X) (6, 7)

Andy Chiu (7):
  riscv: vector: add a comment when calling riscv_setup_vsize()
  riscv: smp: fail booting up smp if inconsistent vlen is detected
  riscv: cpufeature: call match_isa_ext() for single-letter extensions
  riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
  dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description
  riscv: hwprobe: add zve Vector subextensions into hwprobe interface
  riscv: vector: adjust minimum Vector requirement to ZVE32X

 Documentation/arch/riscv/hwprobe.rst          | 15 ++++++
 .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++
 arch/riscv/include/asm/hwcap.h                |  5 ++
 arch/riscv/include/asm/switch_to.h            |  2 +-
 arch/riscv/include/asm/vector.h               | 21 +++++---
 arch/riscv/include/asm/xor.h                  |  2 +-
 arch/riscv/include/uapi/asm/hwprobe.h         |  5 ++
 arch/riscv/kernel/cpufeature.c                | 52 +++++++++++++++++--
 arch/riscv/kernel/head.S                      | 14 ++---
 arch/riscv/kernel/kernel_mode_vector.c        |  4 +-
 arch/riscv/kernel/process.c                   |  4 +-
 arch/riscv/kernel/signal.c                    |  6 +--
 arch/riscv/kernel/smpboot.c                   | 14 +++--
 arch/riscv/kernel/sys_hwprobe.c               | 13 ++++-
 arch/riscv/kernel/vector.c                    | 15 +++---
 arch/riscv/lib/uaccess.S                      |  2 +-
 16 files changed, 162 insertions(+), 42 deletions(-)