| Message ID | 20240325111038.1700-1-jszhang@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: enable lockless lockref implementation | expand |
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Mon, 25 Mar 2024 19:10:36 +0800 you wrote: > This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the > cmpxchg-based lockless lockref implementation for riscv. Then, > implement arch_cmpxchg64_{relaxed|acquire|release}. > > After patch1: > Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. > On JH7110 platform, I see 12.0% improvement. > > [...] Here is the summary with links: - [v3,RESEND,1/2] riscv: select ARCH_USE_CMPXCHG_LOCKREF https://git.kernel.org/riscv/c/eb1e50372946 - [v3,RESEND,2/2] riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} https://git.kernel.org/riscv/c/79d6e4eae966 You are awesome, thank you!
This series selects ARCH_USE_CMPXCHG_LOCKREF to enable the cmpxchg-based lockless lockref implementation for riscv. Then, implement arch_cmpxchg64_{relaxed|acquire|release}. After patch1: Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. On JH7110 platform, I see 12.0% improvement. After patch2: on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] Since v2: - rebase on v6.8-rc1 - collect Reviewed-by tag Since v1: - only select ARCH_USE_CMPXCHG_LOCKREF if 64BIT Jisheng Zhang (2): riscv: select ARCH_USE_CMPXCHG_LOCKREF riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} arch/riscv/Kconfig | 1 + arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+)