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AJvYcCWtMf4FJuEvP9n8YL7Hidewx8A9r7rQfzojyrVFFbBOVwYMPg83VoDbGmoesIPKa9iXmLsoSS5cZB99sGB0gplax715M+hXb46YOrD4jSEQ X-Gm-Message-State: AOJu0YxFuYWsel8RVtG1RI39V9EcxYJRsAUfR4BRYNcSRGS/QXQP5RVx Sxv+ZQHyk8DHC7Dfy/gnZl1m0D/Vx9b2B4KLNfGODS/Pz81ylzlC X-Google-Smtp-Source: AGHT+IGFrBKPW8fc9OizmttpoV1U88eOngqII6WaSNdlGNm5E5Z1fGV98RHkN3M5pqZK8yCujgoIsA== X-Received: by 2002:adf:a1da:0:b0:343:9d3a:cc2e with SMTP id v26-20020adfa1da000000b003439d3acc2emr433983wrv.0.1712176593283; Wed, 03 Apr 2024 13:36:33 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:5eb:3d93:f2b6:25e8]) by smtp.gmail.com with ESMTPSA id p4-20020a05600c468400b00415f496b9b7sm244910wmo.39.2024.04.03.13.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 13:36:32 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, Prabhakar , Lad Prabhakar Subject: [PATCH v2 0/5] Add IAX45 support for RZ/Five SoC Date: Wed, 3 Apr 2024 21:34:58 +0100 Message-Id: <20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_133635_532167_E6EE0882 X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Hi All, The IAX45 block on RZ/Five SoC is almost identical to the IRQC bock found on the RZ/G2L family of SoCs. IAX45 performs various interrupt controls including synchronization for the external interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral interrupts output by each module. And it notifies the interrupt to the PLIC. - Select 32 TINT from 82 GPIOINT. - Integration of bus error interrupts from system bus. - Integration of ECC error interrupts from On-chip RAM. - Indicate interrupt status. (NMI, IRQ, TINT, integrated bus error interrupt and integrated ECC error interrupt) - Setting of interrupt detection method. (NMI, IRQ and TINT) - All interrupts are masked by INTMASK. - Mask function for NMI, IRQ and TINT This patch series adds support for IAX45 in the IRQC driver and enables this on RZ/Five SoC. v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240129151618.90922-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar Lad Prabhakar (5): dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC irqchip/renesas-rzg2l: Add support for RZ/Five SoC riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes .../renesas,rzg2l-irqc.yaml | 17 ++- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 - arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 75 ++++++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 16 -- drivers/irqchip/irq-renesas-rzg2l.c | 137 +++++++++++++++++- 6 files changed, 218 insertions(+), 32 deletions(-)