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Wed, 10 Apr 2024 03:31:55 +0000 Received: from NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn ([fe80::6174:711d:d93:87c9]) by NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn ([fe80::6174:711d:d93:87c9%4]) with mapi id 15.20.7409.053; Wed, 10 Apr 2024 03:31:55 +0000 From: Xingyu Wu To: Michael Turquette , Stephen Boyd , Conor Dooley , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski Cc: Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v4 0/2] Add notifier for PLL0 clock and set it 1.5GHz on Date: Wed, 10 Apr 2024 11:31:46 +0800 Message-Id: <20240410033148.213991-1-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 X-ClientProxiedBy: NT0PR01CA0002.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::23) To NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:8::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NTZPR01MB0956:EE_|NTZPR01MB1132:EE_ X-MS-Office365-Filtering-Correlation-Id: ba8bb759-87f9-45c2-71b5-08dc590ec4f6 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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The first patch is to add the notifier for PLL0 clock. Setting the PLL0 rate need the son clock (cpu_root) to switch its parent clock to OSC clock and switch it back after setting PLL0 rate. It need to use the cpu_root clock from SYSCRG and register the notifier in the SYSCRG driver. The second patch is to set cpu_core rate to 500MHz and PLL0 rate to 1.5GHz to fix the problem about the lower rate of CPUfreq on the visionfive board. The cpu_core clock rate is set to 500MHz first to ensure that the cpu frequency will not suddenly become high and the cpu voltage is not enough to cause a crash when the PLL0 is set to 1.5GHz. The cpu voltage and frequency are then adjusted together by CPUfreq. Changes since v3: - Added the notifier for PLL0 clock. - Set cpu_core rate in DTS v3: https://lore.kernel.org/all/20240402090920.11627-1-xingyu.wu@starfivetech.com/ Changes since v2: - Made the steps into the process into the process of setting PLL0 rate v2: https://lore.kernel.org/all/20230821152915.208366-1-xingyu.wu@starfivetech.com/ Changes since v1: - Added the fixes tag in the commit. v1: https://lore.kernel.org/all/20230811033631.160912-1-xingyu.wu@starfivetech.com/ Xingyu Wu (2): clk: starfive: jh7110-sys: Add notifier for PLL clock riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz .../jh7110-starfive-visionfive-2.dtsi | 6 ++++ .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++++++++++++++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 2 ++ 3 files changed, 38 insertions(+), 1 deletion(-)