| Message ID | 20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Support Zve32[xf] and Zve64[xfd] Vector subextensions | expand |
Hello: This series was applied to riscv/linux.git (fixes) by Palmer Dabbelt <palmer@rivosinc.com>: On Fri, 12 Apr 2024 14:48:56 +0800 you wrote: > The series composes of two parts. The first part provides a quick fix for > the issue on a recent thread[1]. The issue happens when a platform has > ununified vector register length across multiple cores. Specifically, > patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how > vlenb is observed by the system. Patch 2 fixes the issue by failing the > boot process of a secondary core if vlenb mismatches. > > [...] Here is the summary with links: - [v4,1/9] riscv: vector: add a comment when calling riscv_setup_vsize() (no matching commit) - [v4,2/9] riscv: smp: fail booting up smp if inconsistent vlen is detected (no matching commit) - [v4,3/9] riscv: cpufeature: call match_isa_ext() for single-letter extensions (no matching commit) - [v4,4/9] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection (no matching commit) - [v4,5/9] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description (no matching commit) - [v4,6/9] riscv: hwprobe: add zve Vector subextensions into hwprobe interface (no matching commit) - [v4,7/9] riscv: vector: adjust minimum Vector requirement to ZVE32X (no matching commit) - [v4,8/9] hwprobe: fix integer promotion in RISCV_HWPROBE_EXT macro https://git.kernel.org/riscv/c/5ea6764d9095 - [v4,9/9] selftest: run vector prctl test for ZVE32X (no matching commit) You are awesome, thank you!
The series composes of two parts. The first part provides a quick fix for the issue on a recent thread[1]. The issue happens when a platform has ununified vector register length across multiple cores. Specifically, patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how vlenb is observed by the system. Patch 2 fixes the issue by failing the boot process of a secondary core if vlenb mismatches. The second part of the series provide a finer grain view of the Vector extension. Patch 3 give the obsolete ISA parser the ability to expand ISA extensions for sigle letter extensions. Patch 3, 4 introduces Zve32x, Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe. Patch 5 updates all callsites such that Vector subextensions are maximumly supported by the kernel. Two parts of the series are sent together to ease the effort of picking dependency patches. The first part can be merged independent of the second one if necessary. The series is tested on a QEMU and verified that booting, Vector programs context-switch, signal, ptrace, prctl interfaces works when we only report partial V from the ISA. Note that the signal test was performed after applying the commit c27fa53b858b ("riscv: Fix vector state restore in rt_sigreturn()") This patch should be able to apply on risc-v for-next branch on top of the commit ba5ea59f768f ("riscv: Do not save the scratch CSR during suspend") [1]: https://lore.kernel.org/all/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/T/#u Changes in v4: - Add a patch to trigger prctl test on ZVE32X (9) - Add a patch to fix integer promotion bug in hwprobe (8) - Fix a build fail on !CONFIG_RISCV_ISA_V (7) - Add more comment in the assembly code change (2) - Link to v3: https://lore.kernel.org/r/20240318-zve-detection-v3-0-e12d42107fa8@sifive.com Changelog v3: - Include correct maintainers and mailing list into CC. - Cleanup isa string parser code (3) - Adjust extensions order and name (4, 5) - Refine commit message (6) Changelog v2: - Update comments and commit messages (1, 2, 7) - Refine isa_exts[] lists for zve extensions (4) - Add a patch for dt-binding (5) - Make ZVE* extensions depend on has_vector(ZVE32X) (6, 7) --- --- Andy Chiu (9): riscv: vector: add a comment when calling riscv_setup_vsize() riscv: smp: fail booting up smp if inconsistent vlen is detected riscv: cpufeature: call match_isa_ext() for single-letter extensions riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description riscv: hwprobe: add zve Vector subextensions into hwprobe interface riscv: vector: adjust minimum Vector requirement to ZVE32X hwprobe: fix integer promotion in RISCV_HWPROBE_EXT macro selftest: run vector prctl test for ZVE32X Documentation/arch/riscv/hwprobe.rst | 15 ++++++ .../devicetree/bindings/riscv/extensions.yaml | 30 ++++++++++++ arch/riscv/include/asm/hwcap.h | 5 ++ arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 25 ++++++---- arch/riscv/include/asm/xor.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 7 ++- arch/riscv/kernel/cpufeature.c | 56 ++++++++++++++++++---- arch/riscv/kernel/head.S | 19 +++++--- arch/riscv/kernel/kernel_mode_vector.c | 4 +- arch/riscv/kernel/process.c | 4 +- arch/riscv/kernel/signal.c | 6 +-- arch/riscv/kernel/smpboot.c | 14 ++++-- arch/riscv/kernel/sys_hwprobe.c | 13 ++++- arch/riscv/kernel/vector.c | 15 +++--- arch/riscv/lib/uaccess.S | 2 +- .../testing/selftests/riscv/vector/vstate_prctl.c | 6 +-- 17 files changed, 174 insertions(+), 51 deletions(-) --- base-commit: ba5ea59f768f67d127b319b26ba209ff67e0d9a5 change-id: 20240318-zve-detection-50106d2da527 Best regards,