Message ID | 20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com (mailing list archive) |
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Mon, 06 May 2024 21:57:30 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1802:170:6870:7119:e255:c3a0]) by smtp.gmail.com with ESMTPSA id o14-20020a637e4e000000b005f80aced5f3sm8987249pgn.0.2024.05.06.21.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 21:57:29 -0700 (PDT) From: Drew Fustini <dfustini@tenstorrent.com> Subject: [PATCH RFC v3 0/7] clk: thead: Add support for TH1520 AP_SUBSYS clock controller Date: Mon, 06 May 2024 21:55:13 -0700 Message-Id: <20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIADG0OWYC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyjHUUlJIzE vPSU3UzU4B8JSMDIxMDUwNT3ZIMQ1MjA93knGzdJIs0i7Qko9TkNCMLJaCGgqLUtMwKsGHRSkF uzkqxtbUAWlphu2EAAAA= To: Jisheng Zhang <jszhang@kernel.org>, Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>, Yangtao Li <frank.li@vivo.com>, Thomas Bonnefille <thomas.bonnefille@bootlin.com>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu> Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Drew Fustini <dfustini@tenstorrent.com>, Conor Dooley <conor.dooley@microchip.com> X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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clk: thead: Add support for TH1520 AP_SUBSYS clock controller
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This series adds support for the AP sub-system clock controller in the T-Head TH1520 [1]. Yangtao Li originally submitted this series in May 2023 [2]. Jisheng made additional improvements and then passed on the work in progress to me. Changes in RFC v3: - Drop redundant new line and unused clk label from the dts example in the DT binding which I failed to fix in v2. - Add patch [3] from Thomas Bonnefille that fixes dts node ordering in th1520.dtsi. Conor has already merged it into riscv-dt-for-next so the dts patches in this series are based on top of that. - Remove fixed uart clock and converted uart DT nodes to use clocks from the clock controller. - Remove fixed apb clock and converted the dma controller and timer DT nodes to use a clock from the clock controller. - Made ccu_disable_helper() and ccu_enable_helper() to static functions - Follow the advice from Stephen Boyd in Yangtao's original series to not use strings for clk tree topology. Created clk_parent_data arrays to be used with CLK_HW_INIT_PARENTS_DATA instead of parent strings. - Rebase on top of v6.9-rc7 Changes in RFC v2 [4]: - squash the header file patch into the DT schema patch - describe the changes I made to original series in the cover letter instead of the individual patches - fix my typo in my email address Changes in RFC v1 [5] from the original series: - corrected the npu_clk enable bit - deduplicated CLK_NPU and CLK_NPU_AXI number in header - fixed c910_i0_clk reg typo - fixed checkpatch and dt_binding_check warnings - rebased on v6.9-rc5 - revised commit descriptions TODO: This is still marked as an RFC because I still need to make the improvements that Emil suggested in v1: - Input predivider is not handled correctly in ccu_mdiv_recalc_rate(). The PLL multiplies the input frequency and outputs "Foutvco". This is followed by a post divider to produce "Foutpostdiv". However, some clocks derive directly from the "Foutvco". These should be modelled as two differnt clocks. - Use devm_clk_hw_register_gate() for the gates - Use devm_clk_hw_register_mux() for the muxes I'll post a v1 patch once I've addressed the above issues. Thank you, Drew [1] https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [2] https://lore.kernel.org/all/20230515054402.27633-1-frank.li@vivo.com/ [3] https://lore.kernel.org/all/20240425082138.374445-1-thomas.bonnefille@bootlin.com/ [4] https://lore.kernel.org/all/20240426-th1520-clk-v2-v2-0-96b829e6fcee@tenstorrent.com/ [5] https://lore.kernel.org/all/20240110-clk-th1520-v1-0-8b0682567984@tenstorrent.com/ To: Jisheng Zhang <jszhang@kernel.org> To: Guo Ren <guoren@kernel.org> To: Fu Wei <wefu@redhat.com> To: Yangtao Li <frank.li@vivo.com> To: Thomas Bonnefille <thomas.bonnefille@bootlin.com> To: Emil Renner Berthing <emil.renner.berthing@canonical.com> To: Michael Turquette <mturquette@baylibre.com> To: Stephen Boyd <sboyd@kernel.org> To: Rob Herring <robh@kernel.org> To: Krzysztof Kozlowski <krzk+dt@kernel.org> To: Conor Dooley <conor+dt@kernel.org> To: Paul Walmsley <paul.walmsley@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com> To: Albert Ou <aou@eecs.berkeley.edu> Cc: linux-riscv@lists.infradead.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> --- Drew Fustini (6): dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller riscv: dts: thead: change TH1520 uart nodes to use clock controller riscv: dts: thead: change TH1520 mmc nodes to use clock controller riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller Thomas Bonnefille (1): riscv: dts: thead: Fix node ordering in TH1520 device tree .../bindings/clock/thead,th1520-clk-ap.yaml | 64 ++ MAINTAINERS | 3 + arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 12 - .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 12 - arch/riscv/boot/dts/thead/th1520.dtsi | 118 ++- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/thead/Kconfig | 12 + drivers/clk/thead/Makefile | 2 + drivers/clk/thead/clk-th1520-ap.c | 1074 ++++++++++++++++++++ include/dt-bindings/clock/thead,th1520-clk-ap.h | 96 ++ 11 files changed, 1310 insertions(+), 85 deletions(-) --- base-commit: dd5a440a31fae6e459c0d6271dddd62825505361 change-id: 20240505-th1520-clk-b8f8fb2ecf28 Best regards,