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AJvYcCVSBkmYaLJIvY0YaewjkC4oegFvp9G9XpmtmTwsThRRm4Wn2b2Fr1M9Yc3g8XXS3bdqr2dqjj2ydGHsueaO3ukuzQgYVN4N1sG1VwmKR+jv X-Gm-Message-State: AOJu0YzAcfONL8tsqYXYRkMCRBQWb6NdSTCn5R17xv4gAqstPDRXgcsm 4G977N3bBIZXANOWCObzKZhwIi+CeF6Vlg5jNa5jk3UvYjC5JoDTqOZV+Te3kbk= X-Google-Smtp-Source: AGHT+IHZ9jRoKKp0h7NT5gHjkgyTEvRFuMix9kyTJj50uyJt2h4HmefYnbrdEjHmjyVE87F9L6RSOg== X-Received: by 2002:a05:6a21:9988:b0:1af:d0bc:d144 with SMTP id adf61e73a8af0-1afd0bcd40bmr2031451637.53.1715220933069; Wed, 08 May 2024 19:15:33 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0b9d176fsm2339115ad.58.2024.05.08.19.15.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 19:15:32 -0700 (PDT) From: Samuel Holland To: Arnaldo Carvalho de Melo , Palmer Dabbelt , linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Mark Rutland , Adrian Hunter , Alexander Shishkin , Jiri Olsa , Peter Zijlstra , Ingo Molnar , Ian Rogers , Namhyung Kim , Arnaldo Carvalho de Melo , Samuel Holland Subject: [PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events Date: Wed, 8 May 2024 19:14:53 -0700 Message-ID: <20240509021531.680920-1-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240508_191538_261790_B163FECC X-CRM114-Status: GOOD ( 12.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series updates the PMU event JSON files to add support for newer SiFive CPUs, including those used in the upcoming HiFive Premier P550 board. Since most changes are incremental, symbolic links are used when a set of events is unchanged from the previous CPU series. Eric Lin (5): perf vendor events riscv: Update SiFive Bullet events perf vendor events riscv: Add SiFive Bullet version 0x07 events perf vendor events riscv: Add SiFive Bullet version 0x0d events perf vendor events riscv: Add SiFive P550 events perf vendor events riscv: Add SiFive P650 events Samuel Holland (2): perf vendor events riscv: Rename U74 to Bullet perf vendor events riscv: Remove leading zeroes tools/perf/pmu-events/arch/riscv/mapfile.csv | 6 +- .../cycle-and-instruction-count.json | 12 +++ .../arch/riscv/sifive/bullet-07/firmware.json | 1 + .../riscv/sifive/bullet-07/instruction.json | 1 + .../arch/riscv/sifive/bullet-07/memory.json | 1 + .../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++ .../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++ .../cycle-and-instruction-count.json | 1 + .../arch/riscv/sifive/bullet-0d/firmware.json | 1 + .../riscv/sifive/bullet-0d/instruction.json | 1 + .../arch/riscv/sifive/bullet-0d/memory.json | 1 + .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++ .../riscv/sifive/bullet-0d/watchpoint.json | 1 + .../sifive/{u74 => bullet}/firmware.json | 0 .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++ .../arch/riscv/sifive/bullet/memory.json | 32 +++++++ .../arch/riscv/sifive/bullet/microarch.json | 57 ++++++++++++ .../arch/riscv/sifive/p550/firmware.json | 1 + .../arch/riscv/sifive/p550/instruction.json | 1 + .../arch/riscv/sifive/p550/memory.json | 47 ++++++++++ .../arch/riscv/sifive/p550/microarch.json | 1 + .../p650/cycle-and-instruction-count.json | 1 + .../arch/riscv/sifive/p650/firmware.json | 1 + .../arch/riscv/sifive/p650/instruction.json | 1 + .../arch/riscv/sifive/p650/memory.json | 57 ++++++++++++ .../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++ .../arch/riscv/sifive/p650/watchpoint.json | 1 + .../arch/riscv/sifive/u74/instructions.json | 92 ------------------- .../arch/riscv/sifive/u74/memory.json | 32 ------- .../arch/riscv/sifive/u74/microarch.json | 57 ------------ 30 files changed, 555 insertions(+), 182 deletions(-) create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%) create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json