| Message ID | 20240515-add_vlenb_to_dt-v1-0-4ebd7cba0aa1@rivosinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: Allow vlenb to be probed from DT | expand |
On 15 May 2024, at 22:50, Charlie Jenkins <charlie@rivosinc.com> wrote: > > The kernel currently requires all harts to have the same value in the > vlenb csr that is present when a hart supports vector. In order to read > this csr, the kernel needs to boot the hart. Adding vlenb to the DT will > allow the kernel to detect the inconsistency early and not waste time > trying to boot harts that it doesn't support. That doesn’t seem sufficient justification to me. If it can be read from the hardware, why should we have to put it in the FDT? The whole point of the FDT is to communicate the hardware configuration that isn’t otherwise discoverable. As for T-HEAD stuff, if they need it they can have a custom property. Though naively I’d assume there’s a way to avoid it still... Jess
On Wed, May 15, 2024 at 11:25:16PM +0100, Jessica Clarke wrote: > On 15 May 2024, at 22:50, Charlie Jenkins <charlie@rivosinc.com> wrote: > > > > The kernel currently requires all harts to have the same value in the > > vlenb csr that is present when a hart supports vector. In order to read > > this csr, the kernel needs to boot the hart. Adding vlenb to the DT will > > allow the kernel to detect the inconsistency early and not waste time > > trying to boot harts that it doesn't support. > > That doesn’t seem sufficient justification to me. If it can be read > from the hardware, why should we have to put it in the FDT? The whole > point of the FDT is to communicate the hardware configuration that > isn’t otherwise discoverable. Yes you are correct in that vlenb is discoverable on any conforming chip. However, the motivation here is for making decisions about how to boot a hart before it is booted. By placing it in the device tree, we are able to disable vector before the chip is booted instead of trying to boot the chip with vector enabled only to disable it later. In both cases when there is different vlenb on different harts, all harts still boot and the outcome is that vector is disabled. The difference is that with the DT entry, no vector setup code needs to be ran on a booting hart when the outcome will be that vector is not enabled. > > As for T-HEAD stuff, if they need it they can have a custom property. > Though naively I’d assume there’s a way to avoid it still... T-Head does not expose vlenb on all of their chips so I do not know of any other way of getting the vlenb without having it be provided in a DT. That was the motivation for this patch in the first place, but making this available to all vendors allows optimizations to happen during boot. - Charlie > > Jess >
On 16 May 2024, at 00:08, Charlie Jenkins <charlie@rivosinc.com> wrote: > > On Wed, May 15, 2024 at 11:25:16PM +0100, Jessica Clarke wrote: >> On 15 May 2024, at 22:50, Charlie Jenkins <charlie@rivosinc.com> wrote: >>> >>> The kernel currently requires all harts to have the same value in the >>> vlenb csr that is present when a hart supports vector. In order to read >>> this csr, the kernel needs to boot the hart. Adding vlenb to the DT will >>> allow the kernel to detect the inconsistency early and not waste time >>> trying to boot harts that it doesn't support. >> >> That doesn’t seem sufficient justification to me. If it can be read >> from the hardware, why should we have to put it in the FDT? The whole >> point of the FDT is to communicate the hardware configuration that >> isn’t otherwise discoverable. > > Yes you are correct in that vlenb is discoverable on any conforming > chip. However, the motivation here is for making decisions about how to > boot a hart before it is booted. By placing it in the device tree, we > are able to disable vector before the chip is booted instead of trying > to boot the chip with vector enabled only to disable it later. In both > cases when there is different vlenb on different harts, all harts still > boot and the outcome is that vector is disabled. The difference is that > with the DT entry, no vector setup code needs to be ran on a booting > hart when the outcome will be that vector is not enabled. Why does vlen get this special treatment? You could make exactly the same argument for the number of asid bits. The precedent in the kernel, whether RISC-V or other architectures, is to not do this. You can detect it, so you should, especially since optimising for an exceptional, unexpected error case is not worthwhile. >> As for T-HEAD stuff, if they need it they can have a custom property. >> Though naively I’d assume there’s a way to avoid it still... > > T-Head does not expose vlenb on all of their chips so I do not know of > any other way of getting the vlenb without having it be provided in a > DT. That was the motivation for this patch in the first place, but > making this available to all vendors allows optimizations to happen > during boot. How does userspace read it then? But if T-HEAD need it, that means it should be a thead,vlen, not a riscv,vlen. Jess
On Thu, May 16, 2024 at 01:58:29AM +0100, Jessica Clarke wrote: > On 16 May 2024, at 00:08, Charlie Jenkins <charlie@rivosinc.com> wrote: > > > > On Wed, May 15, 2024 at 11:25:16PM +0100, Jessica Clarke wrote: > >> On 15 May 2024, at 22:50, Charlie Jenkins <charlie@rivosinc.com> wrote: > >>> > >>> The kernel currently requires all harts to have the same value in the > >>> vlenb csr that is present when a hart supports vector. In order to read > >>> this csr, the kernel needs to boot the hart. Adding vlenb to the DT will > >>> allow the kernel to detect the inconsistency early and not waste time > >>> trying to boot harts that it doesn't support. > >> > >> That doesn’t seem sufficient justification to me. If it can be read > >> from the hardware, why should we have to put it in the FDT? The whole > >> point of the FDT is to communicate the hardware configuration that > >> isn’t otherwise discoverable. > > > > Yes you are correct in that vlenb is discoverable on any conforming > > chip. However, the motivation here is for making decisions about how to > > boot a hart before it is booted. By placing it in the device tree, we > > are able to disable vector before the chip is booted instead of trying > > to boot the chip with vector enabled only to disable it later. In both > > cases when there is different vlenb on different harts, all harts still > > boot and the outcome is that vector is disabled. The difference is that > > with the DT entry, no vector setup code needs to be ran on a booting > > hart when the outcome will be that vector is not enabled. > > Why does vlen get this special treatment? You could make exactly the > same argument for the number of asid bits. The precedent in the kernel, > whether RISC-V or other architectures, is to not do this. You can > detect it, so you should, especially since optimising for an > exceptional, unexpected error case is not worthwhile. > > >> As for T-HEAD stuff, if they need it they can have a custom property. > >> Though naively I’d assume there’s a way to avoid it still... > > > > T-Head does not expose vlenb on all of their chips so I do not know of > > any other way of getting the vlenb without having it be provided in a > > DT. That was the motivation for this patch in the first place, but > > making this available to all vendors allows optimizations to happen > > during boot. > > How does userspace read it then? But if T-HEAD need it, that means it > should be a thead,vlen, not a riscv,vlen. > > Jess > I'll let Palmer decide if it is reasonable to have vlenb allowed to be placed in the device tree to support cores like ones made by thead which don't support vlenb. Otherwise I will replace it with a thead-specific binding. - Charlie
The kernel currently requires all harts to have the same value in the vlenb csr that is present when a hart supports vector. In order to read this csr, the kernel needs to boot the hart. Adding vlenb to the DT will allow the kernel to detect the inconsistency early and not waste time trying to boot harts that it doesn't support. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- The two patches in this series were previously part of a series "riscv: Support vendor extensions and xtheadvector" but has been factored out due to a lack of reviews on the thead specific parts so that series will be updated separately. --- Charlie Jenkins (1): riscv: vector: Use vlenb from DT Conor Dooley (1): dt-bindings: riscv: cpus: add a vlen register length property Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++ arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/kernel/cpufeature.c | 47 +++++++++++++++++++++++ arch/riscv/kernel/vector.c | 12 +++++- 4 files changed, 66 insertions(+), 1 deletion(-) --- base-commit: a38297e3fb012ddfa7ce0321a7e5a8daeb1872b6 change-id: 20240515-add_vlenb_to_dt-307bb406ecc5