mbox series

[v2,0/2] dt-bindings: interrupt-controller: riscv,cpu-intc

Message ID 20240522153835.22712-1-kanakshilledar111@protonmail.com (mailing list archive)
Headers show
Series dt-bindings: interrupt-controller: riscv,cpu-intc | expand

Message

Kanak Shilledar May 22, 2024, 3:38 p.m. UTC
This series of patches converts the RISC-V CPU interrupt controller to
the newer dt-schema binding.

Patch 1:
This patch is currently at v3 as it has been previously rolled out.
Contains the bindings for the interrupt controller.

Patch 2:
This patch is currently at v2.
Contains the reference to the above interrupt controller. Thus, making
all the RISC-V interrupt controller bindings in a centralized place.

These patches are interdependent.

Kanak Shilledar (2):
  dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
  dt-bindings: riscv: cpus: add ref to interrupt-controller

 .../interrupt-controller/riscv,cpu-intc.txt   | 52 -------------
 .../interrupt-controller/riscv,cpu-intc.yaml  | 73 +++++++++++++++++++
 .../devicetree/bindings/riscv/cpus.yaml       | 21 +-----
 3 files changed, 74 insertions(+), 72 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml


base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23

Comments

Conor Dooley May 22, 2024, 4:04 p.m. UTC | #1
On Wed, May 22, 2024 at 09:08:34PM +0530, Kanak Shilledar wrote:
> This series of patches converts the RISC-V CPU interrupt controller to
> the newer dt-schema binding.
> 
> Patch 1:
> This patch is currently at v3 as it has been previously rolled out.
> Contains the bindings for the interrupt controller.
> 
> Patch 2:
> This patch is currently at v2.
> Contains the reference to the above interrupt controller. Thus, making
> all the RISC-V interrupt controller bindings in a centralized place.o

Don't do this, it breaks tooling:

	b4 shazam 20240522153835.22712-2-kanakshilledar111@protonmail.com
	Grabbing thread from lore.kernel.org/all/20240522153835.22712-2-kanakshilledar111@protonmail.com/t.mbox.gz
	Checking for newer revisions
	Grabbing search results from lore.kernel.org
	Analyzing 3 messages in the thread
	Looking for additional code-review trailers on lore.kernel.org
	Will use the latest revision: v3
	You can pick other revisions using the -vN flag
	Checking attestation on all messages, may take a moment...
	Retrieving CI status, may take a moment...
	---
	  ✓ [PATCH v3 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
	    ✓ Signed: DKIM/gmail.com
	    + Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
	  ERROR: missing [2/2]!
	---
	Total patches: 1
	---
	WARNING: Thread incomplete!
	 Base: using specified base-commit 20cb38a7af88dc40095da7c2c9094da3873fea23
	Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema

If you change one patch in a series, the whole series gets a new version.
Just let git format-patch do that for you with the "-v N" argument and
you'll not have to worry about breaking people's tooling.

Patches themselves are
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.
Kanak Shilledar May 22, 2024, 4:41 p.m. UTC | #2
Hi Conor,

On Wed, May 22, 2024 at 9:34 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Wed, May 22, 2024 at 09:08:34PM +0530, Kanak Shilledar wrote:
> > This series of patches converts the RISC-V CPU interrupt controller to
> > the newer dt-schema binding.
> >
> > Patch 1:
> > This patch is currently at v3 as it has been previously rolled out.
> > Contains the bindings for the interrupt controller.
> >
> > Patch 2:
> > This patch is currently at v2.
> > Contains the reference to the above interrupt controller. Thus, making
> > all the RISC-V interrupt controller bindings in a centralized place.o
>
> Don't do this, it breaks tooling:
>
>         b4 shazam 20240522153835.22712-2-kanakshilledar111@protonmail.com
>         Grabbing thread from lore.kernel.org/all/20240522153835.22712-2-kanakshilledar111@protonmail.com/t.mbox.gz
>         Checking for newer revisions
>         Grabbing search results from lore.kernel.org
>         Analyzing 3 messages in the thread
>         Looking for additional code-review trailers on lore.kernel.org
>         Will use the latest revision: v3
>         You can pick other revisions using the -vN flag
>         Checking attestation on all messages, may take a moment...
>         Retrieving CI status, may take a moment...
>         ---
>           ✓ [PATCH v3 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
>             ✓ Signed: DKIM/gmail.com
>             + Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>           ERROR: missing [2/2]!
>         ---
>         Total patches: 1
>         ---
>         WARNING: Thread incomplete!
>          Base: using specified base-commit 20cb38a7af88dc40095da7c2c9094da3873fea23
>         Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
>
> If you change one patch in a series, the whole series gets a new version.
> Just let git format-patch do that for you with the "-v N" argument and
> you'll not have to worry about breaking people's tooling.

Sorry for the tooling breaking. I used the "-v N" argument to make the
v2 patches but I bumped up the "riscv,cpu-intc"patch
to v3 due to it being in v3 already and it gave errors in the previous
patchset and you mentioned that I missed the v3 in subject line.
How shall I proceed with this version mismatch? Shall I make the
patchset as v3 and have both the patches at v3?

> Patches themselves are
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

I shall include this in my commit message. Is it required to bump the
version of the patch just for the reviewed flag?

> Cheers,
> Conor.

Thanks and Regards,
Kanak Shilledar
Conor Dooley May 22, 2024, 6:26 p.m. UTC | #3
On Wed, May 22, 2024 at 10:11:20PM +0530, Kanak Shilledar wrote:
> Hi Conor,
> 
> On Wed, May 22, 2024 at 9:34 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, May 22, 2024 at 09:08:34PM +0530, Kanak Shilledar wrote:
> > > This series of patches converts the RISC-V CPU interrupt controller to
> > > the newer dt-schema binding.
> > >
> > > Patch 1:
> > > This patch is currently at v3 as it has been previously rolled out.
> > > Contains the bindings for the interrupt controller.
> > >
> > > Patch 2:
> > > This patch is currently at v2.
> > > Contains the reference to the above interrupt controller. Thus, making
> > > all the RISC-V interrupt controller bindings in a centralized place.o
> >
> > Don't do this, it breaks tooling:
> >
> >         b4 shazam 20240522153835.22712-2-kanakshilledar111@protonmail.com
> >         Grabbing thread from lore.kernel.org/all/20240522153835.22712-2-kanakshilledar111@protonmail.com/t.mbox.gz
> >         Checking for newer revisions
> >         Grabbing search results from lore.kernel.org
> >         Analyzing 3 messages in the thread
> >         Looking for additional code-review trailers on lore.kernel.org
> >         Will use the latest revision: v3
> >         You can pick other revisions using the -vN flag
> >         Checking attestation on all messages, may take a moment...
> >         Retrieving CI status, may take a moment...
> >         ---
> >           ✓ [PATCH v3 1/2] dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
> >             ✓ Signed: DKIM/gmail.com
> >             + Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >           ERROR: missing [2/2]!
> >         ---
> >         Total patches: 1
> >         ---
> >         WARNING: Thread incomplete!
> >          Base: using specified base-commit 20cb38a7af88dc40095da7c2c9094da3873fea23
> >         Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema
> >
> > If you change one patch in a series, the whole series gets a new version.
> > Just let git format-patch do that for you with the "-v N" argument and
> > you'll not have to worry about breaking people's tooling.
> 
> Sorry for the tooling breaking. I used the "-v N" argument to make the
> v2 patches but I bumped up the "riscv,cpu-intc"patch
> to v3 due to it being in v3 already and it gave errors in the previous
> patchset and you mentioned that I missed the v3 in subject line.
> How shall I proceed with this version mismatch? Shall I make the
> patchset as v3 and have both the patches at v3?

I would make it "RESEND v3".

> > Patches themselves are
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> I shall include this in my commit message. Is it required to bump the
> version of the patch just for the reviewed flag?

Usually there's no need to resend patches for tags alone. Some people
treat tag-only resubmissions as a "RESEND vN" and others as "vN+1". The
latter is less likely to upset anyone.

Cheers,
Conor.