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([2401:4900:1c28:4b16:65cf:ef28:5753:2be4]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-705ccb3d2acsm3717839b3a.124.2024.06.14.19.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 19:15:19 -0700 (PDT) From: Kanak Shilledar To: Cc: kanakshilledar111@protonmail.com, Kanak Shilledar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [RESEND v4 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc Date: Sat, 15 Jun 2024 07:45:02 +0530 Message-ID: <20240615021507.122035-1-kanakshilledar@gmail.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_191523_138591_37D2D23F X-CRM114-Status: UNSURE ( 8.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series of patches converts the RISC-V CPU interrupt controller to the newer dt-schema binding. Patch 1: This patch is currently at v4 as it has been previously rolled out. Contains the bindings for the interrupt controller. Patch 2: This patch is currently at v4. Contains the reference to the above interrupt controller. Thus, making all the RISC-V interrupt controller bindings in a centralized place. These patches are interdependent. Fixed the patch address mismatch error by changing DCO to @gmail.com Kanak Shilledar (3): dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema dt-bindings: riscv: cpus: add ref to interrupt-controller dt-bindings: serial: vt8500-uart: convert to json-schema .../interrupt-controller/riscv,cpu-intc.txt | 52 ------------- .../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++ .../devicetree/bindings/riscv/cpus.yaml | 21 +----- .../bindings/serial/via,vt8500-uart.yaml | 46 ++++++++++++ .../bindings/serial/vt8500-uart.txt | 27 ------- 5 files changed, 120 insertions(+), 99 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml create mode 100644 Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml delete mode 100644 Documentation/devicetree/bindings/serial/vt8500-uart.txt base-commit: 83a7eefedc9b56fe7bfeff13b6c7356688ffa670