| Message ID | 20241103145153.105097-1-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Zacas/Zabha support and qspinlocks | expand |
> Alexandre Ghiti (11): > riscv: Move cpufeature.h macros into their own header > riscv: Do not fail to build on byte/halfword operations with Zawrs > riscv: Implement cmpxchg32/64() using Zacas > dt-bindings: riscv: Add Zabha ISA extension description > riscv: Implement cmpxchg8/16() using Zabha > riscv: Improve zacas fully-ordered cmpxchg() > riscv: Implement arch_cmpxchg128() using Zacas > riscv: Implement xchg8/16() using Zabha > riscv: Add ISA extension parsing for Ziccrse > dt-bindings: riscv: Add Ziccrse ISA extension description > riscv: Add qspinlock support > > Guo Ren (2): > asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock > asm-generic: ticket-lock: Add separate ticket-lock.h For the series, Reviewed-by: Andrea Parri <parri.andrea@gmail.com> Andrea
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Sun, 3 Nov 2024 15:51:40 +0100 you wrote: > This implements [cmp]xchgXX() macros using Zacas and Zabha extensions > and finally uses those newly introduced macros to add support for > qspinlocks: note that this implementation of qspinlocks satisfies the > forward progress guarantee. > > It also uses Ziccrse to provide the qspinlock implementation. > > [...] Here is the summary with links: - [v6,01/13] riscv: Move cpufeature.h macros into their own header https://git.kernel.org/riscv/c/010e12aa4925 - [v6,02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs https://git.kernel.org/riscv/c/af042c457db0 - [v6,03/13] riscv: Implement cmpxchg32/64() using Zacas https://git.kernel.org/riscv/c/38acdee32d23 - [v6,04/13] dt-bindings: riscv: Add Zabha ISA extension description https://git.kernel.org/riscv/c/51624ddcf59d - [v6,05/13] riscv: Implement cmpxchg8/16() using Zabha https://git.kernel.org/riscv/c/1658ef4314b3 - [v6,06/13] riscv: Improve zacas fully-ordered cmpxchg() https://git.kernel.org/riscv/c/6116e22ef33a - [v6,07/13] riscv: Implement arch_cmpxchg128() using Zacas https://git.kernel.org/riscv/c/f7bd2be7663c - [v6,08/13] riscv: Implement xchg8/16() using Zabha https://git.kernel.org/riscv/c/97ddab7fbea8 - [v6,09/13] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock https://git.kernel.org/riscv/c/cbe82e140bb7 - [v6,10/13] asm-generic: ticket-lock: Add separate ticket-lock.h https://git.kernel.org/riscv/c/22c33321e260 - [v6,11/13] riscv: Add ISA extension parsing for Ziccrse https://git.kernel.org/riscv/c/2d36fe89d872 - [v6,12/13] dt-bindings: riscv: Add Ziccrse ISA extension description https://git.kernel.org/riscv/c/447b2afbcde1 - [v6,13/13] riscv: Add qspinlock support https://git.kernel.org/riscv/c/ab83647fadae You are awesome, thank you!