Message ID | 20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com (mailing list archive) |
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Wed, 15 Jan 2025 10:30:55 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f219f0dsm85333195ad.139.2025.01.15.10.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 10:30:55 -0800 (PST) From: Atish Patra <atishp@rivosinc.com> Subject: [PATCH v2 0/9] Add SBI v3.0 PMU enhancements Date: Wed, 15 Jan 2025 10:30:40 -0800 Message-Id: <20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAND+h2cC/12OQWrDMBBFr2K07gTP2BWSKaX3CME4yriZhaVUc kRKyN2ryJu2oM0TzPvvrhJH4aSG5q4iZ0kSfAF6aZQ7T/6TQU6FFbXUY4sGLst15Mx+HcXPAaz RTOhYH0+dKkeXyLPcqnB/KHyWtIb4Xf0Zn7+bCtH+V2WEFqZ+ttpiTzibjyg5JPFu58KiDo9NH /nrWjLXbUMtnNJUM4fmraoJ6Ze61oyZoLwWDHZsysar1fRH//6MP06JocAi69BkvcMOoqOy/Pg BmvULkCgBAAA= To: Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Mayuresh Chitale <mchitale@ventanamicro.com> Cc: linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt <palmer@rivosinc.com>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Atish Patra <atishp@rivosinc.com> X-Mailer: b4 0.15-dev-13183 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250115_103056_234824_A642B809 X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: <linux-riscv.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-riscv/> List-Post: <mailto:linux-riscv@lists.infradead.org> List-Help: <mailto:linux-riscv-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org |
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Add SBI v3.0 PMU enhancements
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expand
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SBI v3.0 specification[1] added two new improvements to the PMU chaper. 1. Added an additional get_event_info function to query event availablity in bulk instead of individual SBI calls for each event. This helps in improving the boot time. 2. Raw event width allowed by the platform is widened to have 56 bits with RAW event v2 as per new clarification in the priv ISA[2]. Apart from implementing these new features, this series improves the gpa range check in KVM and updates the kvm SBI implementation to SBI v3.0. The opensbi patches have been merged. This series can be found at [4]. This series will conflict with counter delegation patch series[4]. This series is gated on SBI v3.0 freeze requirement while counter delegation series is very early. I will rebase one of them on the other as we gather more reviews and closer to merge. [1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/vv3.0-rc2/riscv-sbi.pdf [2] https://github.com/riscv/riscv-isa-manual/issues/1578 [3] https://github.com/atishp04/linux/tree/b4/pmu_event_info_v2 [4] https://lore.kernel.org/kvm/20250114-counter_delegation-v2-0-8ba74cdb851b@rivosinc.com/ Signed-off-by: Atish Patra <atishp@rivosinc.com> --- Changes in v2: - Dropped PATCH 2 to be taken during rcX. - Improved gpa range check validation by introducing a helper function and checking the entire range. - Link to v1: https://lore.kernel.org/r/20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com --- Atish Patra (9): drivers/perf: riscv: Add SBI v3.0 flag drivers/perf: riscv: Add raw event v2 support RISC-V: KVM: Add support for Raw event v2 drivers/perf: riscv: Implement PMU event info function drivers/perf: riscv: Export PMU event info function KVM: Add a helper function to validate vcpu gpa range RISC-V: KVM: Use the new gpa range validate helper function RISC-V: KVM: Implement get event info function RISC-V: KVM: Upgrade the supported SBI version to 3.0 arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 + arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- arch/riscv/include/asm/sbi.h | 13 +++ arch/riscv/kvm/vcpu_pmu.c | 75 +++++++++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 3 + arch/riscv/kvm/vcpu_sbi_sta.c | 6 +- drivers/perf/riscv_pmu_sbi.c | 190 +++++++++++++++++++++++++--------- include/linux/kvm_host.h | 2 + include/linux/perf/riscv_pmu.h | 2 + virt/kvm/kvm_main.c | 21 ++++ 10 files changed, 258 insertions(+), 59 deletions(-) --- base-commit: e32a80927434907f973f38a88cd19d7e51991d24 change-id: 20241018-pmu_event_info-986e21ce6bd3 -- Regards, Atish patra