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Thu, 8 Feb 2024 08:47:44 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::406a:664b:b8bc:1e6b]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::406a:664b:b8bc:1e6b%2]) with mapi id 15.20.7249.035; Thu, 8 Feb 2024 08:47:44 +0000 From: Inochi Amaoto To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Inochi Amaoto Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v7 0/8] riscv: sophgo: add clock support for Sophgo CV1800/SG2000 SoCs Date: Thu, 8 Feb 2024 16:47:42 +0800 Message-ID: X-Mailer: git-send-email 2.43.0 X-TMN: [McTkfx7ccH6l9onq5zc/paGB+pttV+i3Ucn9JyTaMXWmTVzZE3PYfmo50dRN9OIW] X-ClientProxiedBy: TY1PR01CA0205.jpnprd01.prod.outlook.com (2603:1096:403::35) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20240208084744.1112468-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|CY8PR20MB5985:EE_ X-MS-Office365-Filtering-Correlation-Id: 41df43c5-3882-440d-a50f-08dc28829ded X-Microsoft-Antispam: BCL:0; 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Changed from v6: 1. fix dead lock when setting rate. 2. split the driver patch into several patch for easy reading. Changed from v5: 1. rebased to mainline master tree 2. add SG2000 clock support. 3. fix document link Changed from v4: 1. improve code for patch 2 2. remove the already applied bindings https://lore.kernel.org/all/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com/ Changed from v3: 1. improve comment of patch 3 2. cleanup the include of patch 2 Changed from v2: 1. remove clock-names from bindings. 2. remove clock-frequency node of DT from previous patch. 3. change some unused clock to bypass mode to avoid unlockable PLL. Changed from v1: 1. fix license issues. Inochi Amaoto (8): dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC clk: sophgo: Add CV1800/SG2000 series clock controller driver skeleton clk: sophgo: implement clk_ops for CV1800 series clock controller driver clk: sophgo: Add clock support for CV1800 SoC clk: sophgo: Add clock support for CV1810 SoC clk: sophgo: Add clock support for SG2000 SoC riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC .../bindings/clock/sophgo,cv1800-clk.yaml | 3 +- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 + arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sophgo/Kconfig | 12 + drivers/clk/sophgo/Makefile | 7 + drivers/clk/sophgo/clk-cv1800.c | 1541 +++++++++++++++++ drivers/clk/sophgo/clk-cv1800.h | 123 ++ drivers/clk/sophgo/clk-cv18xx-common.c | 66 + drivers/clk/sophgo/clk-cv18xx-common.h | 81 + drivers/clk/sophgo/clk-cv18xx-ip.c | 887 ++++++++++ drivers/clk/sophgo/clk-cv18xx-ip.h | 261 +++ drivers/clk/sophgo/clk-cv18xx-pll.c | 420 +++++ drivers/clk/sophgo/clk-cv18xx-pll.h | 118 ++ 16 files changed, 3545 insertions(+), 6 deletions(-) create mode 100644 drivers/clk/sophgo/Kconfig create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-cv1800.c create mode 100644 drivers/clk/sophgo/clk-cv1800.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-common.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-ip.h create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.c create mode 100644 drivers/clk/sophgo/clk-cv18xx-pll.h --- 2.43.0