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Fri, 30 Aug 2024 22:39:42 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::ab0b:c0d3:1f91:d149]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::ab0b:c0d3:1f91:d149%4]) with mapi id 15.20.7897.021; Fri, 30 Aug 2024 22:39:42 +0000 From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Haylen Chu Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 0/2] riscv: sophgo: Add pinctrl support for CV1800 series SoC Date: Sat, 31 Aug 2024 06:38:40 +0800 Message-ID: X-Mailer: git-send-email 2.46.0 X-TMN: [GvOITqPhaSUdcV+Vq4ROuqQMlvBo77upmihILKOEtp8=] X-ClientProxiedBy: TYCP301CA0074.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:7d::14) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20240830223841.27471-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|LV8PR20MB7473:EE_ X-MS-Office365-Filtering-Correlation-Id: c6065540-c888-4399-a635-08dcc944a3b5 X-Microsoft-Antispam: BCL:0;ARA:14566002|15080799006|19110799003|5072599009|461199028|8060799006|4302099013|440099028|3412199025|1602099012|1710799026; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add basic pinctrl driver for Sophgo CV1800 series SoCs. This patch series aims to replace the previous patch from Jisheng [1]. Since the pinctrl of cv1800 has nested mux and its pin definination is discrete, it is not suitable to use "pinctrl-single" to cover the pinctrl device. This patch require another patch [2] that provides standard attribute "input-schmitt-microvolt" The v4 version is from [3] Note: As current documentation is not enough to guess the pin configuration of Huashan Pi, only the pinctrl node is added. [1] https://lore.kernel.org/linux-riscv/20231113005702.2467-1-jszhang@kernel.org/ [2] https://lore.kernel.org/all/IA1PR20MB495346246245074234D337A6BBAC2@IA1PR20MB4953.namprd20.prod.outlook.com/ [3] https://lore.kernel.org/all/IA1PR20MB4953DC78BB0FE0C57EA94F91BBB32@IA1PR20MB4953.namprd20.prod.outlook.com/ Changed from v4: 1. remove the alreay applied patch 2. fix 1812h header file problem. Changed from v3: 1. binding: drop unnecessary type 2. binding: use right ref for pin node. 3. binding: remove mixed spaces and tabs. Changed from v2: 1. remove unused export function. 2. drop "drive-strength" and only use "drive-strength-microamp" in the binding. 3. drop unnecessary ref in the binding. 4. drop unnecessary entry for binding example. Changed from v1: 1. replace attribute "sophgo,bus-holder" with standard "bias-bus-hold". 2. replace attribute "input-schmitt" with "input-schmitt-microvolt". 3. add vddio operations support to report pin state. Inochi Amaoto (2): riscv: dts: sophgo: cv1800b: add pinctrl support riscv: dts: sophgo: cv1812h: add pinctrl support .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 49 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++ arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 10 ++++ 3 files changed, 69 insertions(+) --- 2.46.0