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Tue, 16 May 2023 02:40:53 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::4770:9e0f:7f59:1989]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::4770:9e0f:7f59:1989%6]) with mapi id 15.20.6387.021; Tue, 16 May 2023 02:40:52 +0000 From: Inochi Amaoto To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nikita Shubin Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto Subject: [PATCH 0/2] perf: add T-HEAD C9xx series cpu support Date: Tue, 16 May 2023 10:37:12 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 X-TMN: [o7cot8Dg0enCOjpgotPmJWqxekM7KDpBbXMLw5hv+u4=] X-ClientProxiedBy: SI2PR06CA0017.apcprd06.prod.outlook.com (2603:1096:4:186::15) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20230516023714.306240-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|PH7PR20MB4457:EE_ X-MS-Office365-Filtering-Correlation-Id: 68737826-cb09-438c-6a6b-08db55b6f72a X-MS-Exchange-SLBlob-MailProps: mWtqiNqNgRuKO27nt/mZoWqn7+cej2Mk2sWuZ35QmaOBDLAh++ZXCHYw7tg9TcuIPJ3K/Pn8sV8sCEUbEUak6rcV5ncjGh6e+MU+SowpzSohXZM1gSIXNZ9PlBiYKgK+VFY0EOZYKTdqN8IB+MFbWPwHjyomOQ63LvSIb/LsbUR1Jd97PJsTO30Io3+WvDSoAqUMlJr7eMFoF/Iafg8/3v3KjwmyHuBLG+V/5no4abj+Ymnb1+wiWaEoCJ9nwnT6gujb5sjuOuLakiEy6XhbRpoBhYQWs9hA3zrQeYRsFevydREE9fVt2csfbq1sDZCjHSRIspa6Cw7jfPJkwfJnj9C6hCNnsbC/uv0vNq6pPq3WDEVX9h7LVQceTtTByOD0ZR3Lo9aR8QCHtDoDClOOks/fW/KYDB8AWNNOG9sf7URpxJCmENGvBzzndXoAskqpziwX4D83vVaoJGYJ2NFrAqetbUHV1N+N5a76QbNDJjN3ggy5y0cqciI12melYXzdOoyUxDvxIAQGG48uwBctZUqWh71JdjOaMtzqAbSWIHnwP47+T6cnJaoYYRW1epJm+OIf+3f+Eh0hDMyokZIVrYDxnw48orT9vxl/Skn6b4oph0zk7HObvsi+MOGtw9oG+l32XBiEb+1NYAgSUNVff71Z4jRWgw0RsrNVokV24J4t0lfAuVEnX0gQYix6Pv7G4gCOOeGVhpOpudFEqmkMXgWynAlZZ2xK7OPM7uKNG9iPaYcg/gCbQMsZFMZ4fIqJe3k/e51yVUSvCvNcc/ccbPRbJuWZN0ZHcB8XDirhlV8= X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The T-HEAD C9xx series cpu is a series of riscv CPU IP. As this IP was proposed before the current riscv event standard. It has a non-standard events encoding for perf events and unimplemented MARCH and MIMP CSR. This patch add these events to support C9xx cpus. AFAIK, at least the following chips used C9xx cpu. * Allwinner D1 (C906) * T-HEAD th1520 (C910) * Sophgo mango (C920) Inochi Amaoto (2): perf tools riscv: Allow get_cpuid return empty MARCH and MIMP perf vendor events riscv: add T-HEAD C9xx JSON file tools/perf/arch/riscv/util/header.c | 7 +- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../arch/riscv/t-head/c9xx/cache.json | 67 ++++++++++++++++++ .../arch/riscv/t-head/c9xx/firmware.json | 68 +++++++++++++++++++ .../arch/riscv/t-head/c9xx/instruction.json | 22 ++++++ .../arch/riscv/t-head/c9xx/microarch.json | 42 ++++++++++++ 6 files changed, 201 insertions(+), 6 deletions(-) create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json --- 2.40.1