[0/2] RISC-V: some improvements for Atish's framework (for v5)

Message

Tsukasa OI Feb. 16, 2022, 5:04 a.m. UTC

This is patches for Atish's ISA framework patchset v4 (intended to be
squashed into patch 3 and 6 of it).

Changes:
1.  It now skips 'S' and 'U' single-letter "extensions" on QEMU
    (with M/S/U modes) without handling as real extensions.
2.  Split base ISA using minimal parser (not by just splitting with '_',
    find and stop before the first multi-letter extensions, stripping
    version numbers)




Tsukasa OI (2):
  RISC-V: Better 'S' workaround
  RISC-V: Extract base ISA from device tree

 arch/riscv/kernel/cpu.c        | 83 ++++++++++++++++++++++++++++++----
 arch/riscv/kernel/cpufeature.c | 10 ++--
 2 files changed, 81 insertions(+), 12 deletions(-)


base-commit: e9e240c9a854dceb434ceb53bdbe82a657bee5f2