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[0/2] RISC-V: minor fixes to the QEMU workaround in ISA string parser

Message ID cover.1690006695.git.research_trasio@irq.a4lg.com (mailing list archive)
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Series RISC-V: minor fixes to the QEMU workaround in ISA string parser | expand

Message

Tsukasa OI July 22, 2023, 6:22 a.m. UTC
Although hardly functional (mostly editorial), the author hopes this to be
useful to give less confusion to kernel developers and improve
the maintainability of the RISC-V ISA parser, including the QEMU-related
workaround that is "fixed" by this patch set (intended for QEMU < v7.1).

v1:
(the initial submission; see the each PATCH for details)




Tsukasa OI (2):
  RISC-V: make ISA string workaround case-insensitive
  RISC-V: fix the comment for ISA string workaround

 arch/riscv/kernel/cpufeature.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)