Message ID | cover.1731296803.git.unicorn_wang@outlook.com (mailing list archive) |
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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: <linux-riscv.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-riscv/> List-Post: <mailto:linux-riscv@lists.infradead.org> List-Help: <mailto:linux-riscv-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org |
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irqchip: Add Sophgo SG2042 MSI controller
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From: Chen Wang <unicorn_wang@outlook.com> This controller is on the Sophgo SG2042 SoC to transform interrupts from PCIe MSI to PLIC interrupts. Chen Wang (3): dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI irqchip: Add the Sophgo SG2042 MSI interrupt controller riscv: sophgo: dts: add msi controller for SG2042 .../sophgo,sg2042-msi.yaml | 78 ++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 13 + drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sg2042-msi.c | 255 ++++++++++++++++++ 5 files changed, 355 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml create mode 100644 drivers/irqchip/irq-sg2042-msi.c base-commit: 2d5404caa8c7bb5c4e0435f94b28834ae5456623