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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Chen Wang This controller is on the Sophgo SG2042 SoC to transform interrupts from PCIe MSI to PLIC interrupts. Chen Wang (3): dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI irqchip: Add the Sophgo SG2042 MSI interrupt controller riscv: sophgo: dts: add msi controller for SG2042 .../sophgo,sg2042-msi.yaml | 78 ++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 13 + drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sg2042-msi.c | 255 ++++++++++++++++++ 5 files changed, 355 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml create mode 100644 drivers/irqchip/irq-sg2042-msi.c base-commit: 2d5404caa8c7bb5c4e0435f94b28834ae5456623