Show patches with: Series = riscv: ASID-related and UP-related TLB flush enhancements       |   7 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[7/7] riscv: mm: Combine the SMP and non-SMP TLB flushing code riscv: ASID-related and UP-related TLB flush enhancements - - - 24-5 2023-09-09 Samuel Holland Changes Requested
[6/7] riscv: mm: Always flush a single MM context by ASID riscv: ASID-related and UP-related TLB flush enhancements - - - 2225 2023-09-09 Samuel Holland Changes Requested
[5/7] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - 28-1 2023-09-09 Samuel Holland Changes Requested
[4/7] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - 29-1 2023-09-09 Samuel Holland Changes Requested
[3/7] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - 29-1 2023-09-09 Samuel Holland Changes Requested
[2/7] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - 29-1 2023-09-09 Samuel Holland Changes Requested
[1/7] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - 29-1 2023-09-09 Samuel Holland Changes Requested