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Show patches with
: Submitter =
Vincent Chen
| 94 patches
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Apply
Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
irqchip: let the probe of APLIC be earlier than IMSIC
irqchip: let the probe of APLIC be earlier than IMSIC
- - -
13
-
-
2024-08-02
Vincent Chen
Not Applicable
[v6] riscv: mm: execute local TLB flush after populating vmemmap
[v6] riscv: mm: execute local TLB flush after populating vmemmap
- 1 -
13
-
-
2024-01-17
Vincent Chen
Accepted
[v5] riscv: mm: execute local TLB flush after populating vmemmap
[v5] riscv: mm: execute local TLB flush after populating vmemmap
- 1 -
13
-
-
2023-12-20
Vincent Chen
Superseded
[v4] riscv: mm: execute local TLB flush after populating vmemmap
[v4] riscv: mm: execute local TLB flush after populating vmemmap
- - -
-
-
-
2023-12-20
Vincent Chen
Superseded
clocksource: extend the max_delta_ns of timer-riscv and timer-clint to ULONG_MAX
clocksource: extend the max_delta_ns of timer-riscv and timer-clint to ULONG_MAX
- - -
16
-
-
2023-09-05
Vincent Chen
Accepted
[RFC,v1] clocksource: entend the max_delta_ns of timer-riscv andtimer-clint to ULONG_MAX
[RFC,v1] clocksource: entend the max_delta_ns of timer-riscv andtimer-clint to ULONG_MAX
- - -
16
-
-
2023-08-08
Vincent Chen
Changes Requested
[v3] riscv: mm: execute local TLB flush after populating vmemmap
[v3] riscv: mm: execute local TLB flush after populating vmemmap
- 2 -
17
-
-
2023-04-17
Vincent Chen
Changes Requested
riscv: mm: execute local TLB flush after populating vmemmap
riscv: mm: execute local TLB flush after populating vmemmap
- 2 -
17
-
-
2023-04-14
Vincent Chen
Superseded
riscv: mm: execute local TLB flush after populating vmemmap
riscv: mm: execute local TLB flush after populating vmemmap
- 1 -
17
-
-
2023-03-20
Vincent Chen
Superseded
[v4,2/2] rseq/selftests: Add support for RISC-V
RISC-V: add support for restartable sequence
- 1 1
-
-
-
2022-03-08
Vincent Chen
New
[v4,1/2] RISC-V: Add support for restartable sequence
RISC-V: add support for restartable sequence
- 1 -
-
-
-
2022-03-08
Vincent Chen
New
[v3,2/2] rseq/selftests: Add support for RISC-V
RISC-V: add support for restartable sequence
- - 1
-
-
-
2022-03-02
Vincent Chen
New
[v3,1/2] RISC-V: Add support for restartable sequence
RISC-V: add support for restartable sequence
- 1 -
-
-
-
2022-03-02
Vincent Chen
New
[v2] RISC-V: KVM: Refine __kvm_riscv_switch_to() implementation
[v2] RISC-V: KVM: Refine __kvm_riscv_switch_to() implementation
- - -
-
-
-
2022-02-23
Vincent Chen
New
riscv: kvm: refine __kvm_riscv_switch_to and __kvm_riscv_switch_from function
riscv: kvm: refine __kvm_riscv_switch_to and __kvm_riscv_switch_from function
- - -
-
-
-
2022-02-17
Vincent Chen
New
[v2] KVM: RISC-V: Avoid spurious virtual interrupts after clearing hideleg CSR
[v2] KVM: RISC-V: Avoid spurious virtual interrupts after clearing hideleg CSR
- 1 -
-
-
-
2021-12-27
Vincent Chen
New
[v2] riscv: Ensure the value of FP registers in the core dump file is up to date
[v2] riscv: Ensure the value of FP registers in the core dump file is up to date
- 1 -
-
-
-
2021-08-03
Vincent Chen
New
riscv: Ensure the value of FP registers in the core dump file is up to date
riscv: Ensure the value of FP registers in the core dump file is up to date
- - -
-
-
-
2021-08-03
Vincent Chen
New
[v2] riscv: Kconfig: do not select PCI_MSI if CONIFG_PCI is enabled
[v2] riscv: Kconfig: do not select PCI_MSI if CONIFG_PCI is enabled
- 1 -
-
-
-
2021-07-21
Vincent Chen
New
[RFC] riscv: Kconfig: do not select PCI_MSI if CONIFG_PCI is enabled
[RFC] riscv: Kconfig: do not select PCI_MSI if CONIFG_PCI is enabled
- 1 -
-
-
-
2021-07-09
Vincent Chen
New
riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled
riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabled
- - -
-
-
-
2021-05-21
Vincent Chen
New
riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y
riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y
- - -
-
-
-
2021-04-29
Vincent Chen
New
[v3,5/5] riscv: sifive: Apply errata "cip-1200" patch
riscv: introduce alternative mechanism to apply errata patches
- - -
-
-
-
2021-03-22
Vincent Chen
New
[v3,4/5] riscv: sifive: Apply errata "cip-453" patch
riscv: introduce alternative mechanism to apply errata patches
- - -
-
-
-
2021-03-22
Vincent Chen
New
[v3,3/5] riscv: sifive: Add SiFive alternative ports
riscv: introduce alternative mechanism to apply errata patches
- 1 -
-
-
-
2021-03-22
Vincent Chen
New
[v3,2/5] riscv: Introduce alternative mechanism to apply errata solution
riscv: introduce alternative mechanism to apply errata patches
- 1 -
-
-
-
2021-03-22
Vincent Chen
New
[v3,1/5] riscv: Add 3 SBI wrapper functions to get cpu manufacturer information
riscv: introduce alternative mechanism to apply errata patches
- 1 -
-
-
-
2021-03-22
Vincent Chen
New
[v2,5/5] riscv: sifive: Apply errata "cip-1200" patch
riscv: introduce alternative mechanism to apply errata patches
- - -
-
-
-
2021-03-17
Vincent Chen
New
[v2,4/5] riscv: sifive: Apply errata "cip-453" patch
riscv: introduce alternative mechanism to apply errata patches
- - -
-
-
-
2021-03-17
Vincent Chen
New
[v2,3/5] riscv: sifive: Add SiFive alternative ports
riscv: introduce alternative mechanism to apply errata patches
- 1 -
-
-
-
2021-03-17
Vincent Chen
New
[v2,2/5] riscv: Introduce alternative mechanism to apply errata solution
riscv: introduce alternative mechanism to apply errata patches
- 1 -
-
-
-
2021-03-17
Vincent Chen
New
[v2,1/5] riscv: Add 3 SBI wrapper functions to get cpu manufacturer information
riscv: introduce alternative mechanism to apply errata patches
- 1 -
-
-
-
2021-03-17
Vincent Chen
New
[RFC,4/4] riscv: sifive: apply errata "cip-453" patch
riscv: introduce alternative mechanism to apply errata patches
- - -
-
-
-
2021-03-08
Vincent Chen
New
[RFC,3/4] riscv: Introduce alternative mechanism to apply errata solution
riscv: introduce alternative mechanism to apply errata patches
- - -
-
-
-
2021-03-08
Vincent Chen
New
[RFC,2/4] riscv: Get CPU manufacturer information
riscv: introduce alternative mechanism to apply errata patches
- 1 -
-
-
-
2021-03-08
Vincent Chen
New
[RFC,1/4] riscv: Add 3 SBI wrapper functions to get cpu manufacturer information
riscv: introduce alternative mechanism to apply errata patches
- - -
-
-
-
2021-03-08
Vincent Chen
New
[v4,2/2] riscv: set the permission of vdso_data to read-only
riscv: introduce vDSO common flow
- - -
-
-
-
2020-06-09
Vincent Chen
New
[v4,1/2] riscv: use vDSO common flow to reduce the latency of the time-related functions
riscv: introduce vDSO common flow
- 1 -
-
-
-
2020-06-09
Vincent Chen
New
[V5,6/6] riscv: Add SW single-step support for KDB
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-06-01
Vincent Chen
New
[V5,5/6] riscv: Use the XML target descriptions to report 3 system registers
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-06-01
Vincent Chen
New
[V5,4/6] riscv: enable the Kconfig prompt of STRICT_KERNEL_RWX
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-06-01
Vincent Chen
New
[V5,3/6] kgdb: enable arch to support XML packet support.
riscv: Add KGDB and KDB support
1 - -
-
-
-
2020-06-01
Vincent Chen
New
[V5,2/6] riscv: Add KGDB support
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-06-01
Vincent Chen
New
[V5,1/6] kgdb: Add kgdb_has_hit_break function
riscv: Add KGDB and KDB support
1 1 -
-
-
-
2020-06-01
Vincent Chen
New
[v3] riscv: set max_pfn to the PFN of the last page
[v3] riscv: set max_pfn to the PFN of the last page
- 2 1
-
-
-
2020-04-27
Vincent Chen
New
[v2] riscv: set max_pfn to the PFN of the last page
[v2] riscv: set max_pfn to the PFN of the last page
- 2 1
-
-
-
2020-04-27
Vincent Chen
New
riscv: set max_pfn to the PFN of the last page
riscv: set max_pfn to the PFN of the last page
- 3 1
-
-
-
2020-04-23
Vincent Chen
New
[v3,2/2] riscv: set the permission of vdso_data to read-only
riscv: introduce vDSO common flow
- - -
-
-
-
2020-04-23
Vincent Chen
New
[v3,1/2] riscv: use vDSO common flow to reduce the latency of the time-related functions
riscv: introduce vDSO common flow
- 1 -
-
-
-
2020-04-23
Vincent Chen
New
[v2,2/2] riscv: set the permission of vdso_data to read-only
riscv: introduce vDSO common flow
- - -
-
-
-
2020-04-17
Vincent Chen
New
[v2,1/2] riscv: use vDSO common flow to reduce the latency of the time-related functions
riscv: introduce vDSO common flow
- - -
-
-
-
2020-04-17
Vincent Chen
New
[v4,5/5] riscv: Add SW single-step support for KDB
Add KGDB and KDB support
- - -
-
-
-
2020-04-16
Vincent Chen
New
[v4,4/5] riscv: Use the XML target descriptions to report 3 system registers
Add KGDB and KDB support
- - -
-
-
-
2020-04-16
Vincent Chen
New
[v4,3/5] kgdb: enable arch to support XML packet support.
Add KGDB and KDB support
1 - -
-
-
-
2020-04-16
Vincent Chen
New
[v4,2/5] riscv: Add KGDB support
Add KGDB and KDB support
- 1 -
-
-
-
2020-04-16
Vincent Chen
New
[v4,1/5] kgdb: Add kgdb_has_hit_break function
Add KGDB and KDB support
1 1 -
-
-
-
2020-04-16
Vincent Chen
New
riscv: use vDSO common flow to reduce the latency of the time-related functions
riscv: use vDSO common flow to reduce the latency of the time-related functions
- 1 -
-
-
-
2020-04-13
Vincent Chen
New
[v3,5/5] riscv: Add SW single-step support for KDB
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-04-12
Vincent Chen
New
[v3,4/5] riscv: Use the XML target descriptions to report 3 system registers
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-04-12
Vincent Chen
New
[v3,3/5] kgdb: enable arch to support XML packet support.
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-04-12
Vincent Chen
New
[v3,2/5] riscv: Add KGDB support
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-04-12
Vincent Chen
New
[v3,1/5] kgdb: Add kgdb_has_hit_break function
riscv: Add KGDB and KDB support
1 1 -
-
-
-
2020-04-12
Vincent Chen
New
[RFC] riscv: use vDSO common flow to reduce the latency of the time-related functions
[RFC] riscv: use vDSO common flow to reduce the latency of the time-related functions
- - -
-
-
-
2020-04-07
Vincent Chen
New
[v2,5/5] riscv: Add SW single-step support for KDB
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-03-31
Vincent Chen
New
[v2,4/5] riscv: Use the XML target descriptions to report 3 system registers
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-03-31
Vincent Chen
New
[v2,3/5] kgdb: enable arch to support XML packet support.
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-03-31
Vincent Chen
New
[v2,2/5] riscv: Add KGDB support
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-03-31
Vincent Chen
New
[v2,1/5] kgdb: Add kgdb_has_hit_break function
riscv: Add KGDB and KDB support
1 1 -
-
-
-
2020-03-31
Vincent Chen
New
[v2] tty: serial: Add CONSOLE_POLL support to SiFive UART
[v2] tty: serial: Add CONSOLE_POLL support to SiFive UART
- - -
-
-
-
2020-03-18
Vincent Chen
New
[V2,3/3] rseq/selftests: Add support for riscv
riscv: add support for restartable sequence
- - -
-
-
-
2020-03-09
Vincent Chen
New
[V2,2/3] riscv: Add support for restartable sequence
riscv: add support for restartable sequence
- - -
-
-
-
2020-03-09
Vincent Chen
New
[V2,1/3] riscv: add required functions to enable HAVE_REGS_AND_STACK_ACCESS_API
riscv: add support for restartable sequence
- - -
-
-
-
2020-03-09
Vincent Chen
New
[5/5] riscv: Add SW single-step support for KDB
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-03-03
Vincent Chen
New
[4/5] riscv: Use the XML target descriptions to support system registers report
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-03-03
Vincent Chen
New
[3/5] kgdb: enable arch to handle more query packets
riscv: Add KGDB and KDB support
- - -
-
-
-
2020-03-03
Vincent Chen
New
[2/5] riscv: Add KGDB support
riscv: Add KGDB and KDB support
- 1 -
-
-
-
2020-03-03
Vincent Chen
New
[1/5] kgdb: Add kgdb_has_hit_break function
riscv: Add KGDB and KDB support
1 1 -
-
-
-
2020-03-03
Vincent Chen
New
tty: serial: Add CONSOLE_POLL support to SiFive UART
tty: serial: Add CONSOLE_POLL support to SiFive UART
- - -
-
-
-
2020-03-03
Vincent Chen
New
[V2,2/2] riscv: Change code model of module to medany to improve data accessing
solve static percpu symbol issue in module and refine code model of module
- - -
-
-
-
2020-02-21
Vincent Chen
New
[V2,1/2] riscv: avoid the PIC offset of static percpu data in module beyond 2G limits
solve static percpu symbol issue in module and refine code model of module
- - 2
-
-
-
2020-02-21
Vincent Chen
New
[2/2] riscv: Change code model of module to medany to improve data accessing
solve static percpu symbol issue in module and refine code model of module
- - -
-
-
-
2020-02-19
Vincent Chen
New
[1/2] riscv: avoid the PIC offset of static percpu data in module beyond 2G limits
solve static percpu symbol issue in module and refine code model of module
- - 2
-
-
-
2020-02-19
Vincent Chen
New
[3/3] rseq/selftests: Add support for riscv
riscv: add support for restartable sequence
- - -
-
-
-
2019-11-05
Vincent Chen
New
[2/3] riscv: Add support for restartable sequence
riscv: add support for restartable sequence
- - -
-
-
-
2019-11-05
Vincent Chen
New
[1/3] riscv: add required functions to enable HAVE_REGS_AND_STACK_ACCESS_API
riscv: add support for restartable sequence
- - -
-
-
-
2019-11-05
Vincent Chen
New
[4/4] riscv: remove the switch statement in do_trap_break()
riscv: correct the do_trap_break()
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2019-09-23
Vincent Chen
New
[3/4] riscv: Correct the handling of unexpected ebreak in do_trap_break()
riscv: correct the do_trap_break()
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2019-09-23
Vincent Chen
New
[2/4] rsicv: avoid sending a SIGTRAP to a user thread trapped in WARN()
riscv: correct the do_trap_break()
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2019-09-23
Vincent Chen
New
[1/4] riscv: avoid kernel hangs when trapped in BUG()
riscv: correct the do_trap_break()
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2019-09-23
Vincent Chen
New
riscv: Avoid interrupts being erroneously enabled in handle_exception()
riscv: Avoid interrupts being erroneously enabled in handle_exception()
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2019-09-16
Vincent Chen
New
[v2,2/2] riscv: Make __fstate_clean() work correctly.
riscv: Correct the initialized flow of FP and __fstate_clean()
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2019-08-14
Vincent Chen
New
[v2,1/2] riscv: Correct the initialized flow of FP register
riscv: Correct the initialized flow of FP and __fstate_clean()
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2019-08-14
Vincent Chen
New
[2/2] riscv: Make __fstate_clean() can work correctly.
riscv: Correct the initialized flow of FP and __fstate_clean()
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2019-08-08
Vincent Chen
New
[1/2] riscv: Correct the initialized flow of FP register
riscv: Correct the initialized flow of FP and __fstate_clean()
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2019-08-08
Vincent Chen
New