Show patches with: Submitter = Atish Patra       |   26 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,6/6] RISC-V: Do not use cpumask data structure for hartid bitmap Sparse HART id support 1 1 - --- 2021-12-28 Atish Patra New
[v2,5/6] RISC-V: Move spinwait booting method to its own config Sparse HART id support - 1 - --- 2021-12-28 Atish Patra New
[v2,4/6] RISC-V: Move the entire hart selection via lottery to SMP Sparse HART id support - 1 - --- 2021-12-28 Atish Patra New
[v2,3/6] RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method Sparse HART id support - 1 - --- 2021-12-28 Atish Patra New
[v2,2/6] RISC-V: Do not print the SBI version during HSM extension boot print Sparse HART id support - 1 - --- 2021-12-28 Atish Patra New
[v2,1/6] RISC-V: Avoid using per cpu array for ordered booting Sparse HART id support - 1 - --- 2021-12-28 Atish Patra New
[v5,9/9] MAINTAINERS: Add entry for RISC-V PMU drivers Improve RISC-V Perf support using SBI PMU and sscofpmf extension - - - --- 2021-12-25 Atish Patra New
[v5,8/9] Documentation: riscv: Remove the old documentation Improve RISC-V Perf support using SBI PMU and sscofpmf extension - 1 - --- 2021-12-25 Atish Patra New
[v5,7/9] RISC-V: Add sscofpmf extension support Improve RISC-V Perf support using SBI PMU and sscofpmf extension - - - --- 2021-12-25 Atish Patra New
[v5,6/9] RISC-V: Add perf platform driver based on SBI PMU extension Improve RISC-V Perf support using SBI PMU and sscofpmf extension - - - --- 2021-12-25 Atish Patra New
[v5,5/9] RISC-V: Add RISC-V SBI PMU extension definitions Improve RISC-V Perf support using SBI PMU and sscofpmf extension - 1 - --- 2021-12-25 Atish Patra New
[v5,4/9] RISC-V: Add a simple platform driver for RISC-V legacy perf Improve RISC-V Perf support using SBI PMU and sscofpmf extension - 1 - --- 2021-12-25 Atish Patra New
[v5,3/9] RISC-V: Add a perf core library for pmu drivers Improve RISC-V Perf support using SBI PMU and sscofpmf extension - 1 - --- 2021-12-25 Atish Patra New
[v5,2/9] RISC-V: Add CSR encodings for all HPMCOUNTERS Improve RISC-V Perf support using SBI PMU and sscofpmf extension - 1 - --- 2021-12-25 Atish Patra New
[v5,1/9] RISC-V: Remove the current perf implementation Improve RISC-V Perf support using SBI PMU and sscofpmf extension - 1 - --- 2021-12-25 Atish Patra New
[v1,2/2] dt-bindings: riscv: Add DT binding for RISC-V ISA extensions Provide a fraemework for RISC-V ISA extensions - - - --- 2021-12-24 Atish Patra New
[v1,1/2] RISC-V: Provide a framework for parsing multi-letter ISA extensions Provide a fraemework for RISC-V ISA extensions - - - --- 2021-12-24 Atish Patra New
[RFC,6/6] RISC-V: Do not use cpumask data structure for hartid bitmap Sparse HART id support - - - --- 2021-12-04 Atish Patra New
[RFC,5/6] RISC-V: Move spinwait booting method to its own config Sparse HART id support - - - --- 2021-12-04 Atish Patra New
[RFC,4/6] RISC-V: Move the entire hart selection via lottery to SMP Sparse HART id support - 1 - --- 2021-12-04 Atish Patra New
[RFC,3/6] RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method Sparse HART id support - 1 - --- 2021-12-04 Atish Patra New
[RFC,2/6] RISC-V: Do not print the SBI version during HSM extension boot print Sparse HART id support - 1 - --- 2021-12-04 Atish Patra New
[RFC,1/6] RISC-V: Avoid using per cpu array for ordered booting Sparse HART id support - - - --- 2021-12-04 Atish Patra New
[v3] MAINTAINERS: Update Atish's email address [v3] MAINTAINERS: Update Atish's email address - - - --- 2021-12-02 Atish Patra New
[v2] MAINTAINERS: Update Atish's email address [v2] MAINTAINERS: Update Atish's email address - - - --- 2021-11-26 Atish Patra New
MAINTAINERS: Update Atish's email address MAINTAINERS: Update Atish's email address - - - --- 2021-11-18 Atish Patra New