Show patches with: Submitter = Samuel Holland       |    Archived = No       |   296 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v1,3/6] dt-bindings: cache: Add SiFive Extensible Cache controller SiFive cache controller PMU drivers - - - 121- 2024-02-16 Samuel Holland conchuod Changes Requested
[v1,2/6] drivers/perf: Add SiFive Composable Cache PMU driver SiFive cache controller PMU drivers - - - 121- 2024-02-16 Samuel Holland conchuod Changes Requested
[v1,1/6] dt-bindings: cache: Document the sifive,perfmon-counters property SiFive cache controller PMU drivers - - - 13-- 2024-02-16 Samuel Holland conchuod Changes Requested
MAINTAINERS: Update SiFive driver maintainers MAINTAINERS: Update SiFive driver maintainers 3 - - 13-- 2024-02-15 Samuel Holland Accepted
[-fixes,v3,2/2] riscv: Save/restore envcfg CSR during CPU suspend riscv: cbo.zero fixes - 1 - 13-- 2024-02-14 Samuel Holland Superseded
[-fixes,v3,1/2] riscv: Fix enabling cbo.zero when running in M-mode riscv: cbo.zero fixes - 1 - 13-- 2024-02-14 Samuel Holland Superseded
[-fixes,v2,4/4] riscv: Save/restore envcfg CSR during CPU suspend riscv: cbo.zero fixes - - - 13-- 2024-02-13 Samuel Holland Superseded
[-fixes,v2,3/4] riscv: Add ISA extension parsing for Sm and Ss riscv: cbo.zero fixes - - - 13-- 2024-02-13 Samuel Holland Superseded
[-fixes,v2,2/4] dt-bindings: riscv: Add ratified privileged ISA versions riscv: cbo.zero fixes - 1 - 13-- 2024-02-13 Samuel Holland Superseded
[-fixes,v2,1/4] riscv: Fix enabling cbo.zero when running in M-mode riscv: cbo.zero fixes - 1 - 13-- 2024-02-13 Samuel Holland Superseded
[-fixes,2/2] riscv: Save/restore envcfg CSR during CPU suspend [-fixes,1/2] riscv: Fix enabling cbo.zero when running in M-mode - 1 - 913 2024-02-12 Samuel Holland Superseded
[-fixes,1/2] riscv: Fix enabling cbo.zero when running in M-mode [-fixes,1/2] riscv: Fix enabling cbo.zero when running in M-mode - 1 - 12-1 2024-02-12 Samuel Holland Superseded
[v4,12/12] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,11/12] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,10/12] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,09/12] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,08/12] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,07/12] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - 14-- 2024-01-02 Samuel Holland Superseded
[v4,06/12] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - 14-- 2024-01-02 Samuel Holland Superseded
[v4,05/12] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,04/12] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - - - 14-- 2024-01-02 Samuel Holland Superseded
[v4,03/12] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,02/12] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - 1 - 14-- 2024-01-02 Samuel Holland Superseded
[v4,01/12] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - 131- 2024-01-02 Samuel Holland Superseded
[v2,14/14] selftests/fpu: Allow building on other architectures Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,13/14] selftests/fpu: Move FP code to a separate translation unit Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,12/14] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,11/14] drm/amd/display: Only use hard-float, not altivec on powerpc Unified cross-architecture kernel-mode FPU API - - - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,10/14] riscv: Add support for kernel-mode FPU Unified cross-architecture kernel-mode FPU API 1 2 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,09/14] x86: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,08/14] powerpc: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,07/14] LoongArch: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API 1 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,06/14] lib/raid6: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,05/14] arm64: crypto: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,04/14] arm64: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,03/14] ARM: crypto: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,02/14] ARM: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
[v2,01/14] arch: Add ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - --1 2023-12-28 Samuel Holland Handled Elsewhere
dt-bindings: riscv: cpus: Clarify mmu-type interpretation dt-bindings: riscv: cpus: Clarify mmu-type interpretation - 1 - 13-- 2023-12-27 Samuel Holland Accepted
[RFC,12/12] selftests/fpu: Allow building on other architectures Unified cross-architecture kernel-mode FPU API - 1 - 12-1 2023-12-08 Samuel Holland Superseded
[RFC,11/12] selftests/fpu: Move FP code to a separate translation unit Unified cross-architecture kernel-mode FPU API - - - 1111 2023-12-08 Samuel Holland Superseded
[RFC,10/12] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - - - 1012 2023-12-08 Samuel Holland Superseded
[RFC,09/12] riscv: Add support for kernel-mode FPU Unified cross-architecture kernel-mode FPU API - - - 1111 2023-12-08 Samuel Holland Superseded
[RFC,08/12] x86: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - 1111 2023-12-08 Samuel Holland Superseded
[RFC,07/12] powerpc: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - 1111 2023-12-08 Samuel Holland Superseded
[RFC,06/12] LoongArch: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API 1 1 - 12-1 2023-12-08 Samuel Holland Superseded
[RFC,05/12] lib/raid6: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - 12-1 2023-12-08 Samuel Holland Superseded
[RFC,04/12] arm64: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - 1111 2023-12-08 Samuel Holland Superseded
[RFC,03/12] ARM: crypto: Use CC_FLAGS_FPU for NEON CFLAGS Unified cross-architecture kernel-mode FPU API - 1 - 12-1 2023-12-08 Samuel Holland Superseded
[RFC,02/12] ARM: Implement ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - 1111 2023-12-08 Samuel Holland Superseded
[RFC,01/12] arch: Add ARCH_HAS_KERNEL_FPU_SUPPORT Unified cross-architecture kernel-mode FPU API - 1 - 12-1 2023-12-08 Samuel Holland Superseded
[3/3] drm/amd/display: Support DRM_AMD_DC_FP on RISC-V riscv: Add kernel-mode FPU support for amdgpu - - - 11-2 2023-11-22 Samuel Holland Changes Requested
[2/3] riscv: Factor out riscv-march-y to a separate Makefile riscv: Add kernel-mode FPU support for amdgpu - - - 1111 2023-11-22 Samuel Holland Changes Requested
[1/3] riscv: Add support for kernel-mode FPU riscv: Add kernel-mode FPU support for amdgpu - - - 1111 2023-11-22 Samuel Holland Changes Requested
[v3,8/8] riscv: mm: Always use ASID to flush MM contexts riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[v3,7/8] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[v3,6/8] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[v3,5/8] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[v3,4/8] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[v3,3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[v3,2/8] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[v3,1/8] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - - - 13-- 2023-11-22 Samuel Holland Superseded
[3/3] riscv: Use the same CPU operations for all CPUs riscv: CPU operations cleanup - 1 - 13-- 2023-11-21 Samuel Holland Accepted
[2/3] riscv: Remove unused members from struct cpu_operations riscv: CPU operations cleanup - 1 - 13-- 2023-11-21 Samuel Holland Accepted
[1/3] riscv: Deduplicate code in setup_smp() riscv: CPU operations cleanup - 1 - 13-- 2023-11-21 Samuel Holland Accepted
riscv: Remove obsolete rv32_defconfig file riscv: Remove obsolete rv32_defconfig file - 1 - 112- 2023-11-21 Samuel Holland Accepted
riscv: Fix SMP when shadow call stacks are enabled riscv: Fix SMP when shadow call stacks are enabled - 1 - 13-- 2023-11-21 Samuel Holland Accepted
[v2] gpio: sifive: remove unneeded call to platform_set_drvdata() [v2] gpio: sifive: remove unneeded call to platform_set_drvdata() - 2 - 13-- 2023-11-13 Samuel Holland Handled Elsewhere
serial: sifive: Declare PM operations as static serial: sifive: Declare PM operations as static - - - 13-- 2023-11-13 Samuel Holland Handled Elsewhere
[v2,11/11] riscv: mm: Always use ASID to flush MM contexts riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,10/11] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,09/11] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,08/11] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,06/11] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,05/11] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,04/11] riscv: Improve flush_tlb_kernel_range() riscv: ASID-related and UP-related TLB flush enhancements - 1 1 7-6 2023-10-28 Samuel Holland Superseded
[v2,03/11] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: ASID-related and UP-related TLB flush enhancements - 1 1 616 2023-10-28 Samuel Holland Superseded
[v2,02/11] riscv: Improve flush_tlb_range() for hugetlb pages riscv: ASID-related and UP-related TLB flush enhancements - - - 7-6 2023-10-28 Samuel Holland Superseded
[v2,01/11] riscv: Improve tlb_flush() riscv: ASID-related and UP-related TLB flush enhancements - 1 1 7-6 2023-10-28 Samuel Holland Superseded
riscv: Fix CPU feature detection with SMP disabled riscv: Fix CPU feature detection with SMP disabled - 1 - 151- 2023-08-03 Samuel Holland Accepted
[v2,2/2] clk: sifive: Allow building the driver as a module Untitled series #769076 - - - --- 2023-07-25 Samuel Holland Handled Elsewhere
[v3,4/4] gpio: sifive: Allow building the driver as a module gpio: sifive: Module support 1 1 - 16-- 2023-07-25 Samuel Holland Handled Elsewhere
[v3,3/4] gpio: sifive: Get the parent IRQ's domain from its irq_data gpio: sifive: Module support - - - 16-- 2023-07-25 Samuel Holland Handled Elsewhere
[v3,2/4] gpio: sifive: Look up IRQs only once during probe gpio: sifive: Module support - - - 16-- 2023-07-25 Samuel Holland Handled Elsewhere
[v3,1/4] gpio: sifive: Directly use the device's fwnode gpio: sifive: Module support - - - 16-- 2023-07-25 Samuel Holland Handled Elsewhere
[v2,4/4] gpio: sifive: Allow building the driver as a module gpio: sifive: Module support 1 1 - 16-- 2023-07-19 Samuel Holland Superseded
[v2,3/4] gpio: sifive: Get the parent IRQ's domain from its irq_data gpio: sifive: Module support - - - 16-- 2023-07-19 Samuel Holland Superseded
[v2,2/4] gpio: sifive: Look up IRQs only once during probe gpio: sifive: Module support - - - 16-- 2023-07-19 Samuel Holland Superseded
[v2,1/4] gpio: sifive: Directly use the device's fwnode gpio: sifive: Module support - - - 16-- 2023-07-19 Samuel Holland Superseded
[2/2] clk: sifive: Allow building the driver as a module Untitled series #767270 - - - --- 2023-07-17 Samuel Holland Handled Elsewhere
[2/2] gpio: sifive: Allow building the driver as a module gpio: sifive: Module support - - - --- 2023-07-17 Samuel Holland Superseded
irqchip/sifive-plic: Avoid clearing the per-hart enable bits irqchip/sifive-plic: Avoid clearing the per-hart enable bits - - - 16-- 2023-07-17 Samuel Holland Changes Requested
gpio: sifive: Support IRQ wake gpio: sifive: Support IRQ wake - - - 16-- 2023-06-26 Samuel Holland Handled Elsewhere
riscv: Select HAVE_ARCH_USERFAULTFD_MINOR riscv: Select HAVE_ARCH_USERFAULTFD_MINOR - - - 15-1 2023-06-24 Samuel Holland Accepted
serial: sifive: Fix sifive_serial_console_setup() section serial: sifive: Fix sifive_serial_console_setup() section - - - 16-- 2023-06-24 Samuel Holland Handled Elsewhere
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