Show patches with: Submitter = Jesse Taube       |    Archived = No       |   88 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v4,3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 Untitled series #890507 - - - --- 2024-09-15 Jesse Taube New
[v2] RISC-V: hwprobe: Use BIT macro to avoid warnings [v2] RISC-V: hwprobe: Use BIT macro to avoid warnings - 1 1 13-- 2024-08-22 Jesse Taube New
[v9,6/6] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - 1 - 13-- 2024-08-20 Jesse Taube Accepted
[v9,5/6] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 1 - 121- 2024-08-20 Jesse Taube Accepted
[v9,4/6] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - 1 - 121- 2024-08-20 Jesse Taube New
[v9,3/6] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 3 - 13-- 2024-08-20 Jesse Taube Accepted
[v9,2/6] RISC-V: Scalar unaligned access emulated on hotplug CPUs RISC-V: Detect and report speed of unaligned vector accesses - 1 - 13-- 2024-08-20 Jesse Taube Accepted
[v9,1/6] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - 2 - 13-- 2024-08-20 Jesse Taube Accepted
[v8,6/6] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - 1 - 7-6 2024-08-19 Jesse Taube Superseded
[v8,5/6] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 1 - 616 2024-08-19 Jesse Taube Superseded
[v8,4/6] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - 1 - 616 2024-08-19 Jesse Taube Superseded
[v8,3/6] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 3 - 12-1 2024-08-19 Jesse Taube Superseded
[v8,2/6] RISC-V: Scalar unaligned access emulated on hotplug CPUs RISC-V: Detect and report speed of unaligned vector accesses - 1 - 12-1 2024-08-19 Jesse Taube Superseded
[v8,1/6] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - 2 - 12-1 2024-08-19 Jesse Taube Superseded
[v1] RISC-V: hwprobe: Use BIT macro to avoid warnings [v1] RISC-V: hwprobe: Use BIT macro to avoid warnings - 1 1 13-- 2024-08-19 Jesse Taube Superseded
[2/2] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Add Zicclsm extension support 1 1 - 13-- 2024-08-09 Jesse Taube New
[1/2] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Add Zicclsm extension support - 3 1 121- 2024-08-09 Jesse Taube New
[1/1] RISC-V: Add parameter to unaligned access speed [1/1] RISC-V: Add parameter to unaligned access speed - - - --1 2024-08-05 Jesse Taube New
[v7,8/8] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-26 Jesse Taube Superseded
[v7,7/8] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-26 Jesse Taube Superseded
[v7,6/8] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-26 Jesse Taube Superseded
[v7,5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 3 - --1 2024-07-26 Jesse Taube Superseded
[v7,4/8] RISC-V: Scalar unaligned access emulated on hotplug CPUs RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-26 Jesse Taube Superseded
[v7,3/8] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-26 Jesse Taube Superseded
[v7,2/8] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Detect and report speed of unaligned vector accesses 1 - - --1 2024-07-26 Jesse Taube Superseded
[v7,1/8] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-26 Jesse Taube Superseded
[v6,8/8] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-24 Jesse Taube Superseded
[v6,7/8] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-24 Jesse Taube Superseded
[v6,6/8] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-24 Jesse Taube Superseded
[v6,5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 3 - --1 2024-07-24 Jesse Taube Superseded
[v6,4/8] RISC-V: Scalar unaligned access emulated on hotplug CPUs RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-24 Jesse Taube Superseded
[v6,3/8] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-24 Jesse Taube Superseded
[v6,2/8] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Detect and report speed of unaligned vector accesses 1 - - --1 2024-07-24 Jesse Taube Superseded
[v6,1/8] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-24 Jesse Taube Superseded
[v5,7/7] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-17 Jesse Taube Superseded
[v5,6/7] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-17 Jesse Taube Superseded
[v5,5/7] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-17 Jesse Taube Superseded
[v5,4/7] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 3 - --1 2024-07-17 Jesse Taube Superseded
[v5,3/7] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-17 Jesse Taube Superseded
[v5,2/7] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Detect and report speed of unaligned vector accesses 1 - - --1 2024-07-17 Jesse Taube Superseded
[v5,1/7] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-17 Jesse Taube Superseded
[v4,7/7] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-11 Jesse Taube Superseded
[v4,6/7] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-11 Jesse Taube Superseded
[v4,5/7] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-11 Jesse Taube Superseded
[v4,4/7] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-11 Jesse Taube Superseded
[v4,3/7] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-07-11 Jesse Taube Superseded
[v4,2/7] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Detect and report speed of unaligned vector accesses 1 - - --1 2024-07-11 Jesse Taube Superseded
[v4,1/7] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-07-11 Jesse Taube Superseded
[v4,4/4] RISC-V: Use Zkr to seed KASLR base address RISC-V: Parse DT for Zkr to seed KASLR - 3 1 121- 2024-07-09 Jesse Taube Accepted
[v4,3/4] RISC-V: pi: Add kernel/pi/pi.h RISC-V: Parse DT for Zkr to seed KASLR - 1 - 121- 2024-07-09 Jesse Taube Accepted
[v4,2/4] RISC-V: lib: Add pi aliases for string functions RISC-V: Parse DT for Zkr to seed KASLR - 2 - 13-- 2024-07-09 Jesse Taube Accepted
[v4,1/4] RISC-V: pi: Force hidden visibility for all symbol references RISC-V: Parse DT for Zkr to seed KASLR - 1 - 13-- 2024-07-09 Jesse Taube Accepted
[v3,4/4] RISC-V: Use Zkr to seed KASLR base address RISC-V: Parse DT for Zkr to seed KASLR - 2 1 1012 2024-07-01 Jesse Taube Superseded
[v3,3/4] RISC-V: pi: Add kernel/pi/pi.h RISC-V: Parse DT for Zkr to seed KASLR - 1 - 1111 2024-07-01 Jesse Taube Superseded
[v3,2/4] RISC-V: lib: Add pi aliases for string functions RISC-V: Parse DT for Zkr to seed KASLR - 2 - 1111 2024-07-01 Jesse Taube Superseded
[v3,1/4] RISC-V: pi: Force hidden visibility for all symbol references RISC-V: Parse DT for Zkr to seed KASLR - 1 - 12-1 2024-07-01 Jesse Taube Superseded
[v2,3/3] RISC-V: Use Zkr to seed KASLR base address [v2,1/3] RISC-V: pi: Force hidden visibility for all symbol references - - - 1012 2024-06-26 Jesse Taube Changes Requested
[v2,2/3] RISC-V: pi: Add kernel/pi/pi.h [v2,1/3] RISC-V: pi: Force hidden visibility for all symbol references - 1 - 1111 2024-06-26 Jesse Taube Changes Requested
[v2,1/3] RISC-V: pi: Force hidden visibility for all symbol references [v2,1/3] RISC-V: pi: Force hidden visibility for all symbol references - 1 - 12-1 2024-06-26 Jesse Taube Changes Requested
[v3,8/8] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-25 Jesse Taube Superseded
[v3,7/8] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-25 Jesse Taube Superseded
[v3,6/8] RISC-V: Detect unaligned vector accesses supported RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-25 Jesse Taube Superseded
[v3,5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED RISC-V: Detect and report speed of unaligned vector accesses - 1 - --1 2024-06-25 Jesse Taube Superseded
[v3,4/8] RISC-V: Check Zicclsm to set unaligned access speed RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-25 Jesse Taube Superseded
[v3,3/8] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-25 Jesse Taube Superseded
[v3,2/8] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Detect and report speed of unaligned vector accesses 1 - - --1 2024-06-25 Jesse Taube Superseded
[v3,1/8] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-06-25 Jesse Taube Superseded
[v2,6/6] RISC-V: hwprobe: Document unaligned vector perf key RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-13 Jesse Taube Superseded
[v2,5/6] RISC-V: Report vector unaligned access speed hwprobe RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-13 Jesse Taube Superseded
[v2,4/6] RISC-V: Detect unaligned vector accesses supported. RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-13 Jesse Taube Superseded
[v2,3/6] RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect and report speed of unaligned vector accesses - - - --1 2024-06-13 Jesse Taube Superseded
[v2,2/6] dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Detect and report speed of unaligned vector accesses 1 - - --1 2024-06-13 Jesse Taube Superseded
[v2,1/6] RISC-V: Add Zicclsm to cpufeature and hwprobe RISC-V: Detect and report speed of unaligned vector accesses - 2 - --1 2024-06-13 Jesse Taube Superseded
[3/3] RISC-V: Report vector unaligned accesse speed hwprobe [1/3] RISC-V: Add Zicclsm to cpufeature and hwprobe - - - --1 2024-06-06 Jesse Taube Changes Requested
[2/3] RISC-V: Detect unaligned vector accesses supported. [1/3] RISC-V: Add Zicclsm to cpufeature and hwprobe - - - --1 2024-06-06 Jesse Taube Changes Requested
[1/3] RISC-V: Add Zicclsm to cpufeature and hwprobe [1/3] RISC-V: Add Zicclsm to cpufeature and hwprobe - - - --1 2024-06-06 Jesse Taube Changes Requested
RISC-V: fix vector insn load/store width mask RISC-V: fix vector insn load/store width mask - 1 - 13-- 2024-06-06 Jesse Taube Accepted
[RFC,v0] RISCV: Report vector unaligned accesses hwprobe [RFC,v0] RISCV: Report vector unaligned accesses hwprobe - - - 913 2024-06-04 Jesse Taube Changes Requested
[v0] RISC-V: Use Zkr to seed KASLR base address [v0] RISC-V: Use Zkr to seed KASLR base address - - - 715 2024-05-31 Jesse Taube Changes Requested
[v1] RISCV: CANAAN: Make K210_SYSCTL depend on CLK_K210 [v1] RISCV: CANAAN: Make K210_SYSCTL depend on CLK_K210 - 1 - 171- 2023-03-14 Jesse Taube Accepted
[v3,3/3] riscv: configs: Add nommu PHONY defconfig for RV32 Add RISC-V 32 NOMMU support - - - 171- 2023-03-01 Jesse Taube Accepted
[v3,2/3] riscv: Kconfig: Allow RV32 to build with no MMU Add RISC-V 32 NOMMU support - 1 1 18-- 2023-03-01 Jesse Taube Accepted
[v3,1/3] clk: k210: remove an implicit 64-bit division Add RISC-V 32 NOMMU support - 1 - 18-- 2023-03-01 Jesse Taube Handled Elsewhere
[v2,3/3] riscv: configs: Add nommu defconfig for RV32 Add RISC-V 32 NOMMU support - - - 171- 2023-02-12 Jesse Taube palmer Superseded
[v2,2/3] riscv: Kconfig: Allow RV32 to build with no MMU Add RISC-V 32 NOMMU support - - 1 18-- 2023-02-12 Jesse Taube palmer Superseded
[v2,1/3] clk: k210: remove an implicit 64-bit division Add RISC-V 32 NOMMU support - - - 18-- 2023-02-12 Jesse Taube palmer Superseded
[v1,2/2] riscv: configs: Add nommu decfconfig for RV32 Add RISC-V 32 NOMMU support - - - 161- 2023-01-19 Jesse Taube palmer Superseded
[v1,1/2] riscv: Kconfig: Allow RV32 to build with no MMU Add RISC-V 32 NOMMU support - - 1 161- 2023-01-19 Jesse Taube palmer Superseded