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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id d2sm4336919pgp.56.2020.06.12.00.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jun 2020 00:10:25 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, oleg@redhat.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/13] riscv: Add has_vector/riscv_vsize to save vector features. Date: Fri, 12 Jun 2020 15:09:56 +0800 Message-Id: <02932e625077902209ab9967735607f6054cd4d6.1591344965.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200612_001027_559711_32F1BF5D X-CRM114-Status: UNSURE ( 8.72 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:544 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guoren@linux.alibaba.com: add has_vector checking] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c8527d770c98..9b02d8b069e3 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -16,6 +16,10 @@ unsigned long elf_hwcap __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +#ifdef CONFIG_VECTOR +bool has_vector __read_mostly; +unsigned long riscv_vsize __read_mostly; +#endif void riscv_fill_hwcap(void) { @@ -73,4 +77,12 @@ void riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) has_fpu = true; #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + has_vector = true; + /* There are 32 vector registers with vlenb length. */ + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif }