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[220.132.236.182]) by smtp.gmail.com with ESMTPSA id t11sm1806469pjo.21.2020.03.03.00.47.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 03 Mar 2020 00:47:59 -0800 (PST) From: Vincent Chen To: paul.walmsley@sifive.com, palmer@dabbelt.com, jason.wessel@windriver.com, daniel.thompson@linaro.org, dianders@chromium.org Subject: [PATCH 4/5] riscv: Use the XML target descriptions to support system registers report Date: Tue, 3 Mar 2020 16:47:54 +0800 Message-Id: <1583225274-26292-1-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200303_004800_634030_772B52E9 X-CRM114-Status: GOOD ( 13.29 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.3 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1044 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vincent Chen , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org The sstatus, badaddr and scause registers belonged to the thread context, and KGDB can obtain their contents from pt_regs in each trap. However, the sequential number of these registers is far from the general purpose registers. It causes riscv to report many trivial middle registers in the reply packets. In order to solve this problem, the GDB query mechanism was introduced to enable KGDB to customize the reported register list through the XML target descriptions. Signed-off-by: Vincent Chen --- arch/riscv/include/asm/gdb_xml.h | 60 ++++++++++++++++++++++++++++++++++++++++ arch/riscv/include/asm/kgdb.h | 5 +++- arch/riscv/kernel/kgdb.c | 27 ++++++++++++++++++ 3 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/gdb_xml.h diff --git a/arch/riscv/include/asm/gdb_xml.h b/arch/riscv/include/asm/gdb_xml.h new file mode 100644 index 000000000000..42c31f11265c --- /dev/null +++ b/arch/riscv/include/asm/gdb_xml.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +static const char gdb_query_pkt[10] = "Supported:"; + +static const char gdb_reply_feature[64] = + "PacketSize=2048;qXfer:features:read+;"; + +static const char gdb_xfer_read_target[25] = "Xfer:features:read:target"; + +static const char gdb_xfer_read_cpuxml[38] = + "Xfer:features:read:riscv-64bit-cpu.xml"; + +static const char gdb_target_desc[256] = +"l" +"" +"" +"" +""; + +static const char gdb_cpuxml[2048] = +"l" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +""; diff --git a/arch/riscv/include/asm/kgdb.h b/arch/riscv/include/asm/kgdb.h index e3b455932506..67078aec867f 100644 --- a/arch/riscv/include/asm/kgdb.h +++ b/arch/riscv/include/asm/kgdb.h @@ -7,7 +7,7 @@ #define GDB_SIZEOF_REG sizeof(unsigned long) -#define DBG_MAX_REG_NUM (33) +#define DBG_MAX_REG_NUM (36) #define NUMREGBYTES ((DBG_MAX_REG_NUM) * GDB_SIZEOF_REG) #define CACHE_FLUSH_IS_SAFE 1 #define BUFMAX 2048 @@ -66,6 +66,9 @@ static inline void arch_kgdb_breakpoint(void) #define PT_REG_T5 "t5" #define PT_REG_T6 "t6" #define PT_REG_SEPC "pc" +#define PT_REG_SSTATUS "sstatus" +#define PT_REG_STVAL "stval" +#define PT_REG_SCAUSE "scause" #endif #endif diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c index 0a3fe5d672f1..01af9fb43150 100644 --- a/arch/riscv/kernel/kgdb.c +++ b/arch/riscv/kernel/kgdb.c @@ -7,6 +7,7 @@ #include #include #include +#include enum { NOT_KGDB_BREAK = 0, @@ -48,6 +49,9 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = { {PT_REG_T5, GDB_SIZEOF_REG, offsetof(struct pt_regs, t5)}, {PT_REG_T6, GDB_SIZEOF_REG, offsetof(struct pt_regs, t6)}, {PT_REG_SEPC, GDB_SIZEOF_REG, offsetof(struct pt_regs, epc)}, + {PT_REG_SSTATUS, GDB_SIZEOF_REG, offsetof(struct pt_regs, status)}, + {PT_REG_STVAL, GDB_SIZEOF_REG, offsetof(struct pt_regs, badaddr)}, + {PT_REG_SCAUSE, GDB_SIZEOF_REG, offsetof(struct pt_regs, cause)}, }; char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) @@ -100,6 +104,29 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc) regs->epc = pc; } +void kgdb_arch_cmd_query(char *remcom_in_buffer, char *remcom_out_buffer) +{ + switch (remcom_in_buffer[1]) { + case 'S': + if (!strncmp(remcom_in_buffer + 1, + gdb_query_pkt, sizeof(gdb_query_pkt))) + strcpy(remcom_out_buffer, gdb_reply_feature); + break; + case 'X': + if (!strncmp(remcom_in_buffer + 1, + gdb_xfer_read_target, + sizeof(gdb_xfer_read_target))) + strcpy(remcom_out_buffer, gdb_target_desc); + else if (!strncmp(remcom_in_buffer + 1, + gdb_xfer_read_cpuxml, + sizeof(gdb_xfer_read_cpuxml))) + strcpy(remcom_out_buffer, gdb_cpuxml); + break; + default: + break; + } +} + static inline void kgdb_arch_update_addr(struct pt_regs *regs, char *remcom_in_buffer) {