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[123.195.35.41]) by smtp.gmail.com with ESMTPSA id g30sm12097660pgn.40.2020.03.31.08.23.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 Mar 2020 08:23:43 -0700 (PDT) From: Vincent Chen To: jason.wessel@windriver.com, daniel.thompson@linaro.org, dianders@chromium.org, paul.walmsley@sifive.com, palmer@dabbelt.com Subject: [PATCH v2 4/5] riscv: Use the XML target descriptions to report 3 system registers Date: Tue, 31 Mar 2020 23:23:10 +0800 Message-Id: <1585668191-16287-5-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585668191-16287-1-git-send-email-vincent.chen@sifive.com> References: <1585668191-16287-1-git-send-email-vincent.chen@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200331_084438_222428_45F6B0D9 X-CRM114-Status: GOOD ( 15.53 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:e41 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kgdb-bugreport@lists.sourceforge.net, linux-riscv@lists.infradead.org, Vincent Chen Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org The $sstatus, $badaddr, and $scause registers belong to the thread context, so KGDB can obtain their contents from pt_regs in each trap. However, the sequential number of these registers in the gdb register list is far from the general-purpose registers. If riscv port uses the existing method to report these three registers, many trivial registers with sequence numbers in the middle of them will also be packaged to the reply packets. To solve this problem, the riscv port wants to introduce the GDB target description mechanism to customize the reported register list. By the list, the KGDB can ignore the intermediate registers and just reports the general-purpose registers and these three system registers. Signed-off-by: Vincent Chen Reviewed-by: Palmer Dabbelt --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/gdb_xml.h | 117 +++++++++++++++++++++++++++++++++++++++ arch/riscv/include/asm/kgdb.h | 8 ++- arch/riscv/kernel/kgdb.c | 14 +++++ 4 files changed, 139 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/gdb_xml.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 108794f4aa45..94b6f301007c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -67,6 +67,7 @@ config RISCV select HAVE_COPY_THREAD_TLS select HAVE_ARCH_KASAN if MMU && 64BIT select HAVE_ARCH_KGDB + select ARCH_SUPPORTS_GDB_XML config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT diff --git a/arch/riscv/include/asm/gdb_xml.h b/arch/riscv/include/asm/gdb_xml.h new file mode 100644 index 000000000000..1d1459d06a1b --- /dev/null +++ b/arch/riscv/include/asm/gdb_xml.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_GDB_XML_H_ +#define __ASM_GDB_XML_H_ + +#define arch_gdb_stub_feature riscv_gdb_stub_feature +static const char riscv_gdb_stub_feature[64] = + "PacketSize=800;qXfer:features:read+;"; + +static const char gdb_xfer_read_target[31] = "qXfer:features:read:target.xml:"; + +#ifdef CONFIG_64BIT +static const char gdb_xfer_read_cpuxml[39] = + "qXfer:features:read:riscv-64bit-cpu.xml"; + +static const char riscv_gdb_stub_target_desc[256] = +"l" +"" +"" +"" +""; + +static const char riscv_gdb_stub_cpuxml[2048] = +"l" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +""; +#else +static const char gdb_xfer_read_cpuxml[39] = + "qXfer:features:read:riscv-32bit-cpu.xml"; + +static const char riscv_gdb_stub_target_desc[256] = +"l" +"" +"" +"" +""; + +static const char riscv_gdb_stub_cpuxml[2048] = +"l" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +"" +""; +#endif +#endif diff --git a/arch/riscv/include/asm/kgdb.h b/arch/riscv/include/asm/kgdb.h index 69bc6a03081d..6c35a853940d 100644 --- a/arch/riscv/include/asm/kgdb.h +++ b/arch/riscv/include/asm/kgdb.h @@ -7,7 +7,7 @@ #define GDB_SIZEOF_REG sizeof(unsigned long) -#define DBG_MAX_REG_NUM (33) +#define DBG_MAX_REG_NUM (36) #define NUMREGBYTES ((DBG_MAX_REG_NUM) * GDB_SIZEOF_REG) #define CACHE_FLUSH_IS_SAFE 1 #define BUFMAX 2048 @@ -66,6 +66,9 @@ static inline void arch_kgdb_breakpoint(void) #define DBG_REG_T5 "t5" #define DBG_REG_T6 "t6" #define DBG_REG_EPC "pc" +#define DBG_REG_STATUS "sstatus" +#define DBG_REG_BADADDR "stval" +#define DBG_REG_CAUSE "scause" #define DBG_REG_ZERO_OFF 0 #define DBG_REG_RA_OFF 1 @@ -103,5 +106,8 @@ static inline void arch_kgdb_breakpoint(void) #define DBG_REG_STATUS_OFF 33 #define DBG_REG_BADADDR_OFF 34 #define DBG_REG_CAUSE_OFF 35 + +#include + #endif #endif diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c index e3b1075c3935..86d891b7ea2c 100644 --- a/arch/riscv/kernel/kgdb.c +++ b/arch/riscv/kernel/kgdb.c @@ -7,6 +7,7 @@ #include #include #include +#include enum { NOT_KGDB_BREAK = 0, @@ -48,6 +49,9 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = { {DBG_REG_T5, GDB_SIZEOF_REG, offsetof(struct pt_regs, t5)}, {DBG_REG_T6, GDB_SIZEOF_REG, offsetof(struct pt_regs, t6)}, {DBG_REG_EPC, GDB_SIZEOF_REG, offsetof(struct pt_regs, epc)}, + {DBG_REG_STATUS, GDB_SIZEOF_REG, offsetof(struct pt_regs, status)}, + {DBG_REG_BADADDR, GDB_SIZEOF_REG, offsetof(struct pt_regs, badaddr)}, + {DBG_REG_CAUSE, GDB_SIZEOF_REG, offsetof(struct pt_regs, cause)}, }; char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs) @@ -100,6 +104,16 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc) regs->epc = pc; } +void arch_handle_qxfer_pkt(char *remcom_in_buffer, char *remcom_out_buffer) +{ + if (!strncmp(remcom_in_buffer, gdb_xfer_read_target, + sizeof(gdb_xfer_read_target))) + strcpy(remcom_out_buffer, riscv_gdb_stub_target_desc); + else if (!strncmp(remcom_in_buffer, gdb_xfer_read_cpuxml, + sizeof(gdb_xfer_read_cpuxml))) + strcpy(remcom_out_buffer, riscv_gdb_stub_cpuxml); +} + static inline void kgdb_arch_update_addr(struct pt_regs *regs, char *remcom_in_buffer) {