| Message ID | 20190618061216.7303-1-palmer@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: Take a third shot at describing sfence.vma | expand |
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 54fee0cadb1e..8fda8974d8c7 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -19,8 +19,9 @@ #include <asm/smp.h> /* - * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction - * cache as well, so a 'fence.i' is not necessary. + * Flush entire local TLB. 'sfence.vma' enforces that all subsequent memory + * accesses, both from the instruction and data streams, respect all previously + * installed mappings. Thus we do not need a fence.i here. */ static inline void local_flush_tlb_all(void) {
This is the third iteration of this comment. I've had the diff floating around for a while since someone pointed out that the original version didn't make any sense, but I forgot who pointed this out. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> --- arch/riscv/include/asm/tlbflush.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)