| Message ID | 20190807151009.31971-1-hch@lst.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: move sifive_l2_cache.c to drivers/misc | expand |
On Wed, Aug 07, 2019 at 06:10:09PM +0300, Christoph Hellwig wrote: > The sifive_l2_cache.c is in no way related to RISC-V architecture > memory management. It is a little stub driver working around the fact > that the EDAC maintainers prefer their drivers to be structured in a > certain way that doesn't fit the SiFive SOCs. > > Move the file to drivers/misc and only build it when the EDAC_SIFIVE > config option is selected. > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > arch/riscv/mm/Makefile | 1 - > drivers/misc/Makefile | 1 + > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > 3 files changed, 1 insertion(+), 1 deletion(-) > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) Why isn't this in drivers/edac/ ? why is this a misc driver? Seems like it should sit next to the edac stuff. thanks, greg k-h
On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > --- > > arch/riscv/mm/Makefile | 1 - > > drivers/misc/Makefile | 1 + > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > 3 files changed, 1 insertion(+), 1 deletion(-) > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > Why isn't this in drivers/edac/ ? > why is this a misc driver? Seems like it should sit next to the edac > stuff. No idea. EDAC maintainers, would you object to taking what is currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
On Wed, 7 Aug 2019, Christoph Hellwig wrote: > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > > --- > > > arch/riscv/mm/Makefile | 1 - > > > drivers/misc/Makefile | 1 + > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > > 3 files changed, 1 insertion(+), 1 deletion(-) > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > > > Why isn't this in drivers/edac/ ? > > why is this a misc driver? Seems like it should sit next to the edac > > stuff. > > No idea. EDAC maintainers, would you object to taking what is > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? If this driver is moved out of arch/riscv/mm, it should ideally go into some sort of common L2 cache controller driver directory, along with other L2 cache controller drivers like arch/arm/mm/*l2c*. Like many L2 cache controllers, this controller also supports cache flushing operations and SoC-specific way operations. We just don't use those on RISC-V - yet. - Paul
On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote: > On Wed, 7 Aug 2019, Christoph Hellwig wrote: > > > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > > > --- > > > > arch/riscv/mm/Makefile | 1 - > > > > drivers/misc/Makefile | 1 + > > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > > > 3 files changed, 1 insertion(+), 1 deletion(-) > > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > > > > > Why isn't this in drivers/edac/ ? > > > why is this a misc driver? Seems like it should sit next to the edac > > > stuff. > > > > No idea. EDAC maintainers, would you object to taking what is > > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? > > If this driver is moved out of arch/riscv/mm, it should ideally go into > some sort of common L2 cache controller driver directory, along > with other L2 cache controller drivers like arch/arm/mm/*l2c*. > > Like many L2 cache controllers, this controller also supports cache > flushing operations and SoC-specific way operations. We just don't use > those on RISC-V - yet. Well, another reason to not have it under arch/riscv/ as it is a SOC specific driver, which we all have somewhere else, just like arm64 and new arm ports do. And especially not unconditionally built.
On Thu, Aug 8, 2019 at 9:50 AM Christoph Hellwig <hch@lst.de> wrote: > On Wed, Aug 07, 2019 at 08:40:58AM -0700, Paul Walmsley wrote: > > On Wed, 7 Aug 2019, Christoph Hellwig wrote: > > > On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote: > > > > > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") > > > > > Signed-off-by: Christoph Hellwig <hch@lst.de> > > > > > --- > > > > > arch/riscv/mm/Makefile | 1 - > > > > > drivers/misc/Makefile | 1 + > > > > > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 > > > > > 3 files changed, 1 insertion(+), 1 deletion(-) > > > > > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%) > > > > > > > > Why isn't this in drivers/edac/ ? > > > > why is this a misc driver? Seems like it should sit next to the edac > > > > stuff. > > > > > > No idea. EDAC maintainers, would you object to taking what is > > > currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ? > > > > If this driver is moved out of arch/riscv/mm, it should ideally go into > > some sort of common L2 cache controller driver directory, along > > with other L2 cache controller drivers like arch/arm/mm/*l2c*. > > > > Like many L2 cache controllers, this controller also supports cache > > flushing operations and SoC-specific way operations. We just don't use > > those on RISC-V - yet. > > Well, another reason to not have it under arch/riscv/ as it is a SOC > specific driver, which we all have somewhere else, just like arm64 > and new arm ports do. And especially not unconditionally built. soc specific drivers that don't have their own subsystem can go into drivers/soc/$VENDOR/. For this driver, I would also think that the edac subsystem is the best fit. Right now, the driver is split in two halves: there is drivers/edac/sifive_edac.c and arch/riscv/mm/sifive_l2_cache.c, with neither of those working without the other. Moving both into a single file would seem to allow simplifying it as a proper 'platform_driver', which the drivers/edac side today is not (it just registers a platform device in its module_init call). Arnd
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 74055e1d6f21..d2101d0741d4 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -11,6 +11,5 @@ obj-y += extable.o obj-y += ioremap.o obj-y += cacheflush.o obj-y += context.o -obj-y += sifive_l2_cache.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index abd8ae249746..886d48301e8e 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -59,3 +59,4 @@ obj-y += cardreader/ obj-$(CONFIG_PVPANIC) += pvpanic.o obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o +obj-$(CONFIG_EDAC_SIFIVE) += sifive_l2_cache.o diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/misc/sifive_l2_cache.c similarity index 100% rename from arch/riscv/mm/sifive_l2_cache.c rename to drivers/misc/sifive_l2_cache.c
The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/misc and only build it when the EDAC_SIFIVE config option is selected. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/mm/Makefile | 1 - drivers/misc/Makefile | 1 + {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)