| Message ID | 20200309110211.91130-5-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | New RISC-V Local Interrupt Controller Driver | expand |
Fixed Marc's email address. On Mon, Mar 9, 2020 at 4:33 PM Anup Patel <anup.patel@wdc.com> wrote: > > Instead of directly calling RISC-V timer interrupt handler from > RISC-V local interrupt conntroller driver, this patch implements > RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs > of Linux IRQ subsystem. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > --- > arch/riscv/include/asm/irq.h | 2 - > drivers/clocksource/timer-riscv.c | 79 ++++++++++++++++++++----------- > drivers/irqchip/irq-riscv-intc.c | 8 ---- > 3 files changed, 52 insertions(+), 37 deletions(-) > > diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h > index a9e5f07a7e9c..9807ad164015 100644 > --- a/arch/riscv/include/asm/irq.h > +++ b/arch/riscv/include/asm/irq.h > @@ -10,8 +10,6 @@ > #include <linux/interrupt.h> > #include <linux/linkage.h> > > -void riscv_timer_interrupt(void); > - > #include <asm-generic/irq.h> > > #endif /* _ASM_RISCV_IRQ_H */ > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index c4f15c4068c0..6b82f2e41f8e 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -14,7 +14,10 @@ > #include <linux/irq.h> > #include <linux/sched_clock.h> > #include <linux/io-64-nonatomic-lo-hi.h> > -#include <asm/smp.h> > +#include <linux/irqdomain.h> > +#include <linux/interrupt.h> > +#include <linux/of.h> > +#include <linux/of_irq.h> > #include <asm/sbi.h> > > u64 __iomem *riscv_time_cmp; > @@ -39,6 +42,7 @@ static int riscv_clock_next_event(unsigned long delta, > return 0; > } > > +static unsigned int riscv_clock_event_irq; > static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = { > .name = "riscv_timer_clockevent", > .features = CLOCK_EVT_FEAT_ONESHOT, > @@ -74,65 +78,86 @@ static int riscv_timer_starting_cpu(unsigned int cpu) > struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu); > > ce->cpumask = cpumask_of(cpu); > + ce->irq = riscv_clock_event_irq; > clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); > > - csr_set(CSR_IE, IE_TIE); > + enable_percpu_irq(riscv_clock_event_irq, > + irq_get_trigger_type(riscv_clock_event_irq)); > return 0; > } > > static int riscv_timer_dying_cpu(unsigned int cpu) > { > - csr_clear(CSR_IE, IE_TIE); > + disable_percpu_irq(riscv_clock_event_irq); > return 0; > } > > /* called directly from the low-level interrupt handler */ > -void riscv_timer_interrupt(void) > +static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) > { > struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event); > > csr_clear(CSR_IE, IE_TIE); > evdev->event_handler(evdev); > + > + return IRQ_HANDLED; > } > > static int __init riscv_timer_init_dt(struct device_node *n) > { > - int cpuid, hartid, error; > - > - hartid = riscv_of_processor_hartid(n); > - if (hartid < 0) { > - pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", > - n, hartid); > - return hartid; > - } > - > - cpuid = riscv_hartid_to_cpuid(hartid); > - if (cpuid < 0) { > - pr_warn("Invalid cpuid for hartid [%d]\n", hartid); > - return cpuid; > - } > - > - if (cpuid != smp_processor_id()) > + int error; > + struct of_phandle_args oirq; > + > + /* > + * Either we have one INTC DT node under each CPU DT node > + * or a single system wide INTC DT node. Irrespective to > + * number of INTC DT nodes, we only proceed if we are able > + * to find irq_domain of INTC. > + * > + * Once we have INTC irq_domain, we create mapping for timer > + * interrupt HWIRQ and request_percpu_irq() on it. > + */ > + > + if (!irq_find_host(n) || riscv_clock_event_irq) > return 0; > > - pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", > - __func__, cpuid, hartid); > + oirq.np = n; > + oirq.args_count = 1; > + oirq.args[0] = RV_IRQ_TIMER; > + riscv_clock_event_irq = irq_create_of_mapping(&oirq); > + if (!riscv_clock_event_irq) > + return -ENODEV; > + > error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); > if (error) { > - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > - error, cpuid); > + pr_err("registering clocksource failed [%d]\n", error); > return error; > } > > sched_clock_register(riscv_sched_clock, 64, riscv_timebase); > > + error = request_percpu_irq(riscv_clock_event_irq, > + riscv_timer_interrupt, > + "riscv-timer", &riscv_clock_event); > + if (error) { > + pr_err("registering percpu irq failed [%d]\n", error); > + return error; > + } > + > error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, > "clockevents/riscv/timer:starting", > riscv_timer_starting_cpu, riscv_timer_dying_cpu); > - if (error) > + if (error) { > pr_err("cpu hp setup state failed for RISCV timer [%d]\n", > error); > - return error; > + return error; > + } > + > + pr_info("running at %lu.%02luMHz frequency\n", > + (unsigned long)riscv_timebase / 1000000, > + (unsigned long)(riscv_timebase / 10000) % 100); > + > + return 0; > } > > -TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); > +TIMER_OF_DECLARE(riscv_timer, "riscv,cpu-intc", riscv_timer_init_dt); > diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > index e8f7af6dd3c2..93d9d2a38059 100644 > --- a/drivers/irqchip/irq-riscv-intc.c > +++ b/drivers/irqchip/irq-riscv-intc.c > @@ -20,20 +20,12 @@ static struct irq_domain *intc_domain; > > static asmlinkage void riscv_intc_irq(struct pt_regs *regs) > { > - struct pt_regs *old_regs; > unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; > > if (unlikely(cause >= BITS_PER_LONG)) > panic("unexpected interrupt cause"); > > switch (cause) { > - case RV_IRQ_TIMER: > - old_regs = set_irq_regs(regs); > - irq_enter(); > - riscv_timer_interrupt(); > - irq_exit(); > - set_irq_regs(old_regs); > - break; > #ifdef CONFIG_SMP > case RV_IRQ_SOFT: > /* > -- > 2.17.1 >
diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index a9e5f07a7e9c..9807ad164015 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -10,8 +10,6 @@ #include <linux/interrupt.h> #include <linux/linkage.h> -void riscv_timer_interrupt(void); - #include <asm-generic/irq.h> #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index c4f15c4068c0..6b82f2e41f8e 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -14,7 +14,10 @@ #include <linux/irq.h> #include <linux/sched_clock.h> #include <linux/io-64-nonatomic-lo-hi.h> -#include <asm/smp.h> +#include <linux/irqdomain.h> +#include <linux/interrupt.h> +#include <linux/of.h> +#include <linux/of_irq.h> #include <asm/sbi.h> u64 __iomem *riscv_time_cmp; @@ -39,6 +42,7 @@ static int riscv_clock_next_event(unsigned long delta, return 0; } +static unsigned int riscv_clock_event_irq; static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = { .name = "riscv_timer_clockevent", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -74,65 +78,86 @@ static int riscv_timer_starting_cpu(unsigned int cpu) struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu); ce->cpumask = cpumask_of(cpu); + ce->irq = riscv_clock_event_irq; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); - csr_set(CSR_IE, IE_TIE); + enable_percpu_irq(riscv_clock_event_irq, + irq_get_trigger_type(riscv_clock_event_irq)); return 0; } static int riscv_timer_dying_cpu(unsigned int cpu) { - csr_clear(CSR_IE, IE_TIE); + disable_percpu_irq(riscv_clock_event_irq); return 0; } /* called directly from the low-level interrupt handler */ -void riscv_timer_interrupt(void) +static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event); csr_clear(CSR_IE, IE_TIE); evdev->event_handler(evdev); + + return IRQ_HANDLED; } static int __init riscv_timer_init_dt(struct device_node *n) { - int cpuid, hartid, error; - - hartid = riscv_of_processor_hartid(n); - if (hartid < 0) { - pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", - n, hartid); - return hartid; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%d]\n", hartid); - return cpuid; - } - - if (cpuid != smp_processor_id()) + int error; + struct of_phandle_args oirq; + + /* + * Either we have one INTC DT node under each CPU DT node + * or a single system wide INTC DT node. Irrespective to + * number of INTC DT nodes, we only proceed if we are able + * to find irq_domain of INTC. + * + * Once we have INTC irq_domain, we create mapping for timer + * interrupt HWIRQ and request_percpu_irq() on it. + */ + + if (!irq_find_host(n) || riscv_clock_event_irq) return 0; - pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", - __func__, cpuid, hartid); + oirq.np = n; + oirq.args_count = 1; + oirq.args[0] = RV_IRQ_TIMER; + riscv_clock_event_irq = irq_create_of_mapping(&oirq); + if (!riscv_clock_event_irq) + return -ENODEV; + error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("registering clocksource failed [%d]\n", error); return error; } sched_clock_register(riscv_sched_clock, 64, riscv_timebase); + error = request_percpu_irq(riscv_clock_event_irq, + riscv_timer_interrupt, + "riscv-timer", &riscv_clock_event); + if (error) { + pr_err("registering percpu irq failed [%d]\n", error); + return error; + } + error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, "clockevents/riscv/timer:starting", riscv_timer_starting_cpu, riscv_timer_dying_cpu); - if (error) + if (error) { pr_err("cpu hp setup state failed for RISCV timer [%d]\n", error); - return error; + return error; + } + + pr_info("running at %lu.%02luMHz frequency\n", + (unsigned long)riscv_timebase / 1000000, + (unsigned long)(riscv_timebase / 10000) % 100); + + return 0; } -TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); +TIMER_OF_DECLARE(riscv_timer, "riscv,cpu-intc", riscv_timer_init_dt); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8f7af6dd3c2..93d9d2a38059 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -20,20 +20,12 @@ static struct irq_domain *intc_domain; static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { - struct pt_regs *old_regs; unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; if (unlikely(cause >= BITS_PER_LONG)) panic("unexpected interrupt cause"); switch (cause) { - case RV_IRQ_TIMER: - old_regs = set_irq_regs(regs); - irq_enter(); - riscv_timer_interrupt(); - irq_exit(); - set_irq_regs(old_regs); - break; #ifdef CONFIG_SMP case RV_IRQ_SOFT: /*
Instead of directly calling RISC-V timer interrupt handler from RISC-V local interrupt conntroller driver, this patch implements RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs of Linux IRQ subsystem. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- arch/riscv/include/asm/irq.h | 2 - drivers/clocksource/timer-riscv.c | 79 ++++++++++++++++++++----------- drivers/irqchip/irq-riscv-intc.c | 8 ---- 3 files changed, 52 insertions(+), 37 deletions(-)