From patchwork Sun May 10 07:54:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Hellwig X-Patchwork-Id: 11538965 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43B701668 for ; Sun, 10 May 2020 07:58:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 216C72070B for ; Sun, 10 May 2020 07:58:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Vl77ustz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 216C72070B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date :Subject:To:From:Reply-To:Content-Type:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=INn4CtVqYhB5mCs8+6rhyM+JLlbdj/x9vTgOvRuFchU=; b=Vl77ustzeAqnjn 3QrWwNLITOSHq/YVOTxilp5sMEwQWQm8G7Mw1KTvLC1aAfL41ww2cJP685zCSIb97Z00VwFnUatot I6/ILc1NMKZky0HThssPUd3btPF3Y2QbKTP+ccU7Y4DoPKdWU9r4gKcyK5vVrl4KQFR6z+b+myjlK 0yXk2cuL/AvgNjZB6PlVpRco2RtgbcR66LOgP1/HAnFyBhJcCDQFfLsRrD7WaSSBMv5c04ErmjLbJ 9U4R9SWhPSfnSQ24g18CbdjPUVxzY/DEZTpkNxyg+gR4UN4qD9JvRG0dSiAtQ6tZA7JtyXpZD+Vnx jGPMBe7Z9uVHUthnWzqQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jXgrC-0003ZU-8R; Sun, 10 May 2020 07:58:42 +0000 Received: from [2001:4bb8:180:9d3f:c70:4a89:bc61:2] (helo=localhost) by bombadil.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1jXgoD-00089Q-95; Sun, 10 May 2020 07:55:38 +0000 From: Christoph Hellwig To: Andrew Morton , Arnd Bergmann , Roman Zippel Subject: [PATCH 08/31] asm-generic: don't include in cacheflush.h Date: Sun, 10 May 2020 09:54:47 +0200 Message-Id: <20200510075510.987823-9-hch@lst.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200510075510.987823-1-hch@lst.de> References: <20200510075510.987823-1-hch@lst.de> MIME-Version: 1.0 X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org, Michal Simek , Jessica Yu , linux-ia64@vger.kernel.org, linux-c6x-dev@linux-c6x.org, linux-sh@vger.kernel.org, linux-hexagon@vger.kernel.org, x86@kernel.org, linux-um@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-mm@kvack.org, linux-m68k@lists.linux-m68k.org, openrisc@lists.librecores.org, linux-alpha@vger.kernel.org, sparclinux@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This seems to lead to some crazy include loops when using asm-generic/cacheflush.h on more architectures, so leave it to the arch header for now. Signed-off-by: Christoph Hellwig --- arch/um/include/asm/tlb.h | 2 ++ arch/x86/include/asm/cacheflush.h | 2 ++ include/asm-generic/cacheflush.h | 3 --- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/um/include/asm/tlb.h b/arch/um/include/asm/tlb.h index 70ee603839006..ff9c62828962c 100644 --- a/arch/um/include/asm/tlb.h +++ b/arch/um/include/asm/tlb.h @@ -2,6 +2,8 @@ #ifndef __UM_TLB_H #define __UM_TLB_H +#include + #include #include #include diff --git a/arch/x86/include/asm/cacheflush.h b/arch/x86/include/asm/cacheflush.h index 63feaf2a5f93d..b192d917a6d0b 100644 --- a/arch/x86/include/asm/cacheflush.h +++ b/arch/x86/include/asm/cacheflush.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_CACHEFLUSH_H #define _ASM_X86_CACHEFLUSH_H +#include + /* Caches aren't brain-dead on the intel. */ #include #include diff --git a/include/asm-generic/cacheflush.h b/include/asm-generic/cacheflush.h index 906277492ec59..bf9bb83e9fc8d 100644 --- a/include/asm-generic/cacheflush.h +++ b/include/asm-generic/cacheflush.h @@ -2,9 +2,6 @@ #ifndef _ASM_GENERIC_CACHEFLUSH_H #define _ASM_GENERIC_CACHEFLUSH_H -/* Keep includes the same across arches. */ -#include - #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 /*