| Message ID | 20200518091441.94843-2-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | More improvements for multiple PLICs | expand |
On Mon, 18 May 2020 02:14:39 PDT (-0700), Anup Patel wrote: > For multiple PLIC instances, each PLIC can only target a subset of > CPUs which is represented by "lmask" in the "struct plic_priv". > > Currently, the default irq affinity for each PLIC interrupt is all > online CPUs which is illegal value for default irq affinity when we > have multiple PLIC instances. To fix this, we now set "lmask" as the > default irq affinity in for each interrupt in plic_irqdomain_map(). > > Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs") > Cc: stable@vger.kernel.org > Signed-off-by: Anup Patel <anup.patel@wdc.com> > --- > drivers/irqchip/irq-sifive-plic.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > index 822e074c0600..9f7f8ce88c00 100644 > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -176,9 +176,12 @@ static struct irq_chip plic_chip = { > static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > irq_hw_number_t hwirq) > { > + struct plic_priv *priv = d->host_data; > + > irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, > handle_fasteoi_irq, NULL, NULL); If you're going to re-spin this, d->host_data could be priv here. > irq_set_noprobe(irq); > + irq_set_affinity(irq, &priv->lmask); > return 0; > } Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
On Fri, May 22, 2020 at 3:36 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Mon, 18 May 2020 02:14:39 PDT (-0700), Anup Patel wrote: > > For multiple PLIC instances, each PLIC can only target a subset of > > CPUs which is represented by "lmask" in the "struct plic_priv". > > > > Currently, the default irq affinity for each PLIC interrupt is all > > online CPUs which is illegal value for default irq affinity when we > > have multiple PLIC instances. To fix this, we now set "lmask" as the > > default irq affinity in for each interrupt in plic_irqdomain_map(). > > > > Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs") > > Cc: stable@vger.kernel.org > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > > --- > > drivers/irqchip/irq-sifive-plic.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index 822e074c0600..9f7f8ce88c00 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -176,9 +176,12 @@ static struct irq_chip plic_chip = { > > static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, > > irq_hw_number_t hwirq) > > { > > + struct plic_priv *priv = d->host_data; > > + > > irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, > > handle_fasteoi_irq, NULL, NULL); > > If you're going to re-spin this, d->host_data could be priv here. The controller's private data is named "host_data" for "struct irq_domain" in Linux irq subsystem hence the usage. > > > irq_set_noprobe(irq); > > + irq_set_affinity(irq, &priv->lmask); > > return 0; > > } > > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> > Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Thanks, Anup
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 822e074c0600..9f7f8ce88c00 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -176,9 +176,12 @@ static struct irq_chip plic_chip = { static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct plic_priv *priv = d->host_data; + irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_noprobe(irq); + irq_set_affinity(irq, &priv->lmask); return 0; }
For multiple PLIC instances, each PLIC can only target a subset of CPUs which is represented by "lmask" in the "struct plic_priv". Currently, the default irq affinity for each PLIC interrupt is all online CPUs which is illegal value for default irq affinity when we have multiple PLIC instances. To fix this, we now set "lmask" as the default irq affinity in for each interrupt in plic_irqdomain_map(). Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs") Cc: stable@vger.kernel.org Signed-off-by: Anup Patel <anup.patel@wdc.com> --- drivers/irqchip/irq-sifive-plic.c | 3 +++ 1 file changed, 3 insertions(+)