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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id m15sm7661069qkp.76.2021.12.24.13.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Dec 2021 13:16:48 -0800 (PST) From: Atish Patra X-Google-Original-From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v1 2/2] dt-bindings: riscv: Add DT binding for RISC-V ISA extensions Date: Fri, 24 Dec 2021 13:16:32 -0800 Message-Id: <20211224211632.1698523-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211224211632.1698523-1-atishp@rivosinc.com> References: <20211224211632.1698523-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211224_131649_566460_B0E43790 X-CRM114-Status: UNSURE ( 9.40 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org RISC-V ISA extensions can be single letter or multi-letter names. The single letter extensions are mostly base extensions and encoded in "riscv,isa" DT property. However, parsing the multi-letter extensions via the isa string is cumbersome and is not scalable. Add a new DT node for multi-letter extensions. Signed-off-by: Atish Patra --- Documentation/devicetree/bindings/riscv/cpus.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index aa5fb64d57eb..6c4eecf389a9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -78,6 +78,15 @@ properties: - rv64imac - rv64imafdc + riscv,isa-ext: + description: + Identifies the specific RISC-V instruction set architecture extensions + supported by one or multiple harts. All the multi-letter extensions + should be listed here as a boolean property. This subnode can be under + /cpus or under individual cpu node. In case of former, it represent + the common ISA extensions for all harts. The name of the boolean property + must match the actual ISA extension name in all lowercase format. + $ref: "/schemas/types.yaml#/definitions/boolean" # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false