From patchwork Mon Jan 17 11:07:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12715186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CFFFC433FE for ; Mon, 17 Jan 2022 11:07:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NP8av2gAjEb3brGPvXexF13Nc4Cn30Bo7xeoH3KE6zk=; b=dg888NxCgd+MFZ QcBRUV7PXxIbPjV7St/tsrtvRNbhONMI9KnQlFDHd+0M8YzZFtONr3KNlfF0G5/56g+nlP1NtKWDa cL2NpeLLx/ZpuhR1bxw8v79LRTsbvthZvAM8YLk1jqPfRHbwmrRgKBtEcXiLia75TfHGZlz3beXOp 7rgzeVgERurhAEc5GHypny2YSUG6fsEIDx7DMwOg17+1jm6ZoqHR1YNQBmBcbP7IU0/IYQddtb6Qo FbwEezUtbdRzcxsVeBCK8D+0C/sYqF879IszaiZDRxNo66uvK96sKPlZLo80U9hoPIjHcKKjBP7/G KZakgQCCod+jqFPOcBOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9Pqp-00EbGK-Cs; Mon, 17 Jan 2022 11:07:03 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n9Pqm-00Eb8U-BI for linux-riscv@lists.infradead.org; Mon, 17 Jan 2022 11:07:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642417620; x=1673953620; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kM9r1xW/DHGqgb4EQRJlkwePmu9HkhIfNKIm9H/2uhU=; b=gynnwEx86HClbEdJtS4gOcRV7W60mr5Gh7XlFYosnOFQ2zy8OrhzPP3t fOSfjHSwVXOyFdX2ee/nE6kcQeStDGLpPIdR+FLGgaAG6UVMbpDHq0a46 tA5mgLcD9KSm3Cu66/GM0CvWv/gFccr0haUq4zpsDazXvJj4A/ivmXhtU ToBCTXx+8enYzsjvxLtF+aGs/+6H+n2EVj5VEBrNDBSYXWlMNelhIJoS0 /qfRzyxuXcUsnnwQFFCCwam3iesRFv0blg2YmaXlcmmcya3//2Aj0BtxL GhUI8pzcd6Z3BWxB+jhlxhnUn8IH5ePqo/rF75qIa26lm83dINWiAcn5d g==; IronPort-SDR: rL7MqIuYxT/nV8q++65dJNBx1ujqOnv2+nEcs4KeIpuTq1aMXzh10f8x0jP/7NWtJ5X8e4Fwiv qO47FFq5+lTGcJvd0xFFT+kvhJ2XNE04sSa3l8ELxufC5EYjMRbb310HC8bjndBau6CS6+8Pqd 1cg3FZ41uy1+F5LM4OIJSYgj6pFE5uDjKp2x7idr2oybylDfktaj1O3JSoTdkN7Z2tqI3C2X7S mK13tmQZ9WNHsPlMgNX9BA4uD0cTPi94aedNevmJAWAjgYydBur/iYryfm26YEGXEzUhyUvvCn JIQQU0A6row2myBbV+x1OktE X-IronPort-AV: E=Sophos;i="5.88,295,1635231600"; d="scan'208";a="82713566" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Jan 2022 04:06:59 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 17 Jan 2022 04:06:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 17 Jan 2022 04:06:52 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 10/14] riscv: dts: microchip: add fpga fabric section to icicle kit Date: Mon, 17 Jan 2022 11:07:51 +0000 Message-ID: <20220117110755.3433142-11-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220117110755.3433142-1-conor.dooley@microchip.com> References: <20220117110755.3433142-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220117_030700_526046_A4F833EB X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Split the device tree for the Microchip MPFS into two sections by adding microchip-mpfs-fabric.dtsi, which contains peripherals contained in the FPGA fabric. Signed-off-by: Conor Dooley --- .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 +++++++++++++++++++ .../microchip/microchip-mpfs-icicle-kit.dts | 8 ++++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 1 + 3 files changed, 34 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi new file mode 100644 index 000000000000..c1dcd56b0679 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + core_pwm0: pwm@41000000 { + compatible = "microchip,corepwm-rtl-v4"; + reg = <0x0 0x41000000 0x0 0xF0>; + microchip,sync-update = /bits/ 16 <0>; + #pwm-cells = <2>; + clocks = <&clkcfg CLK_FIC3>; + status = "disabled"; + }; + + i2c2: i2c@44000000 { + compatible = "microchip,corei2c-rtl-v7"; + reg = <0x0 0x44000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkcfg CLK_FIC3>; + interrupt-parent = <&plic>; + interrupts = <122>; + clock-frequency = <100000>; + status = "disabled"; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 6d19ba196f12..ab803f71626a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -68,6 +68,10 @@ &mmc { sd-uhs-sdr104; }; +&i2c2 { + status = "okay"; +}; + &emac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; @@ -86,3 +90,7 @@ phy1: ethernet-phy@9 { ti,fifo-depth = <0x01>; }; }; + +&core_pwm0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 717e39b30a15..c7d73756c9b8 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -3,6 +3,7 @@ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" +#include "microchip-mpfs-fabric.dtsi" / { #address-cells = <2>;