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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip ip core PWM controller bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description: |
+ corePWM is an 16 channel pulse width modulator FPGA IP
+
+ https://www.microsemi.com/existing-parts/parts/152118
+
+properties:
+ compatible:
+ items:
+ - const: microchip,corepwm-rtl-v4
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ microchip,sync-update:
+ description: |
+ In synchronous mode, all channels are updated at the beginning of the PWM period.
+ Asynchronous mode is relevant to applications such as LED control, where
+ synchronous updates are not required. Asynchronous mode lowers the area size,
+ reducing shadow register requirements. This can be set at run time, provided
+ SHADOW_REG_EN is asserted. SHADOW_REG_EN is set by the FPGA bitstream programmed
+ to the device.
+ Each bit corresponds to a PWM channel & represents whether synchronous mode is
+ possible for the PWM channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint16
+ default: 0
+
+ microchip,dac-mode:
+ description: |
+ Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
+ a minimum period pulse train whose High/Low average is that of the chosen duty
+ cycle. This "DAC" will have far better bandwidth and ripple performance than the
+ standard PWM algorithm can achieve.
+ Each bit corresponds to a PWM channel & represents whether dac mode is enabled
+ that PWM channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint16
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#pwm-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ microchip,sync-update = /bits/ 16 <0>;
+ clocks = <&clkcfg CLK_FIC3>;
+ reg = <0x41000000 0xF0>;
+ #pwm-cells = <2>;
+ };