From patchwork Mon Jan 31 11:47:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12730574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E49ABC433F5 for ; Mon, 31 Jan 2022 11:46:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gmd6lp4cGZuSV+5iMGJK0HHoZq4bIzmidNRdd3Y9XE8=; b=S3Qbfuguw9risl 6MWO6S3a+SNAOY9t1FyuugeKYxqprgl8ZOOa3ORk5Iec/E/SuzekUFr3oSKD/JTPcZTx/38fQY7yq jHk3TYY3+ra+ItZDOi8CG1YvaJUsveaVF9DffswywRbsERWIp3pxptdeIbkLuCYvyc8zFRTLhXylS zYzh/yCqBQzWtM8fV1jJFEmhRgdEkJF+JszSKg/3HjvVD9QRY08jkJQQz1CKfBtUbI9aZpMHr0FN/ xCvorWZRR9UF7OFOLTVQ7W8BZAXRDFpfXhmD0k4bb9+amyHiOIcvac4fBzmZuOCrpx17chFtHqZ5z 6ZKRa2RnKFP9A6nRb8uw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nEV8J-009BpT-9k; Mon, 31 Jan 2022 11:46:07 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nEV8C-009Bjv-Mx for linux-riscv@lists.infradead.org; Mon, 31 Jan 2022 11:46:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1643629560; x=1675165560; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CHRZOpuL/m9qzVgModijBDCCLSMHHYovHwMK3VqF6rM=; b=1Um3beXpa3Zf1uqasAAFuE/8QcvcNRlcOdPeE04fBf1qqp/tuHgtkf/E D+GBIsfGTYe7kkpkGboIK6d9cMkKF191Z8Vdi+GqAjLC5lZH03BRur1Xx TNqyBOphvTAJzw7EhWGp0x5blnUTrrDUNC767SRd/9w48dxj+DR8fjEAT sJ2T5gISu0A8pxnA7h3OFPDcf/20ZWVf5MrQs9zfr/bH1fCq0/wVQL1yJ ENbxVNfinHLL2KjJVeiSbZbFGJU3HxlAQKSpzCeMw2as6Pjt1jZjhsiFR VGCJdHTOqpf2mia7TykIiYysROFSqM+N3t71bE/Oki2mA7zD+j5Lz/aWW Q==; IronPort-SDR: 81mI5yQ+eopGG6f8m6IRL/uSCNiP05eBifqKcJWoBKLU4+kwH58K8zKfaniYuVN33Vwx8vhK/W /Vhm9gsqh/fGVxiyn97slcVQmLFGR3eepMZzSxp1MbcrllJhdIHzWWsISpL3b76vTKTxgzWDIJ lbdpeoRv6GqOFHFuk5c84Xp6wZ7UXhCC3KajzpXoi1l1vmNXOXbkAcmf8dSdYM2Xed5ldIMVA3 XGHS1g7EepcurI/Yu5EcSO8iTAWPlwBMJf+Xelg1LQIX5+b8u2iNHgd8mELmtHkUoVvi41jc8i 72lHYAN5Xv9Rrv94y2PAfoDZ X-IronPort-AV: E=Sophos;i="5.88,330,1635231600"; d="scan'208";a="160544975" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 31 Jan 2022 04:45:59 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 31 Jan 2022 04:45:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 31 Jan 2022 04:45:53 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Rob Herring Subject: [PATCH v5 05/12] dt-bindings: gpio: add bindings for microchip mpfs gpio Date: Mon, 31 Jan 2022 11:47:20 +0000 Message-ID: <20220131114726.973690-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.0 In-Reply-To: <20220131114726.973690-1-conor.dooley@microchip.com> References: <20220131114726.973690-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220131_034600_818884_498009C3 X-CRM114-Status: GOOD ( 10.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add device tree bindings for the gpio controller on the Microchip PolarFire SoC. Reviewed-by: Rob Herring Signed-off-by: Conor Dooley --- .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml new file mode 100644 index 000000000000..47a76f0e32b9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS GPIO Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +properties: + compatible: + items: + - enum: + - microchip,mpfs-gpio + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt mapping, one per GPIO. Maximum 32 GPIOs. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + "#interrupt-cells": + const: 1 + + ngpios: + description: + The number of GPIOs available. + minimum: 1 + maximum: 32 + default: 32 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - interrupt-controller + - "#gpio-cells" + - gpio-controller + - clocks + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x20122000 0x1000>; + clocks = <&clkcfg CLK_GPIO2>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + }; +...