diff mbox series

[V5,15/21] riscv: compat: Add hw capability check for elf

Message ID 20220201150545.1512822-16-guoren@kernel.org (mailing list archive)
State New, archived
Headers show
Series riscv: compat: Add COMPAT mode support for rv64 | expand

Commit Message

Guo Ren Feb. 1, 2022, 3:05 p.m. UTC 
From: Guo Ren <guoren@linux.alibaba.com>

Detect hardware COMPAT (32bit U-mode) capability in rv64. If not
support COMPAT mode in hw, compat_elf_check_arch would return
false by compat_binfmt_elf.c

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/include/asm/elf.h |  3 ++-
 arch/riscv/kernel/process.c  | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 1 deletion(-)

Comments

Guo Ren Feb. 2, 2022, 2:02 a.m. UTC | #1 
On Tue, Feb 1, 2022 at 11:07 PM <guoren@kernel.org> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Detect hardware COMPAT (32bit U-mode) capability in rv64. If not
> support COMPAT mode in hw, compat_elf_check_arch would return
> false by compat_binfmt_elf.c
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Christoph Hellwig <hch@lst.de>
> ---
>  arch/riscv/include/asm/elf.h |  3 ++-
>  arch/riscv/kernel/process.c  | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
> index aee40040917b..3a4293dc7229 100644
> --- a/arch/riscv/include/asm/elf.h
> +++ b/arch/riscv/include/asm/elf.h
> @@ -40,7 +40,8 @@
>   * elf64_hdr e_machine's offset are different. The checker is
>   * a little bit simple compare to other architectures.
>   */
> -#define compat_elf_check_arch(x) ((x)->e_machine == EM_RISCV)
> +extern bool compat_elf_check_arch(Elf32_Ehdr *hdr);
> +#define compat_elf_check_arch  compat_elf_check_arch
>
>  #define CORE_DUMP_USE_REGSET
>  #define ELF_EXEC_PAGESIZE      (PAGE_SIZE)
> diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> index 1a666ad299b4..758847cba391 100644
> --- a/arch/riscv/kernel/process.c
> +++ b/arch/riscv/kernel/process.c
> @@ -83,6 +83,38 @@ void show_regs(struct pt_regs *regs)
>                 dump_backtrace(regs, NULL, KERN_DEFAULT);
>  }
>
> +#ifdef CONFIG_COMPAT
> +static bool compat_mode_support __read_mostly;
> +
> +bool compat_elf_check_arch(Elf32_Ehdr *hdr)
> +{
> +       if (compat_mode_support && (hdr->e_machine == EM_RISCV))
> +               return true;
> +       else
> +               return false;
> +}
> +
> +static int compat_mode_detect(void)
Forgot __init, here

> +{
> +       unsigned long tmp = csr_read(CSR_STATUS);
> +
> +       csr_write(CSR_STATUS, (tmp & ~SR_UXL) | SR_UXL_32);
> +
> +       if ((csr_read(CSR_STATUS) & SR_UXL) != SR_UXL_32) {
> +               pr_info("riscv: 32bit compat mode detect failed\n");
> +               compat_mode_support = false;
> +       } else {
> +               compat_mode_support = true;
> +               pr_info("riscv: 32bit compat mode detected\n");
> +       }
> +
> +       csr_write(CSR_STATUS, tmp);
> +
> +       return 0;
> +}
> +arch_initcall(compat_mode_detect);
> +#endif
> +
>  void start_thread(struct pt_regs *regs, unsigned long pc,
>         unsigned long sp)
>  {
> --
> 2.25.1
>
Christoph Hellwig Feb. 2, 2022, 7:51 a.m. UTC | #2 
On Tue, Feb 01, 2022 at 11:05:39PM +0800, guoren@kernel.org wrote:
> +bool compat_elf_check_arch(Elf32_Ehdr *hdr)
> +{
> +	if (compat_mode_support && (hdr->e_machine == EM_RISCV))
> +		return true;
> +	else
> +		return false;
> +}

This can be simplified to:

	return compat_mode_support && hdr->e_machine == EM_RISCV;

I'd also rename compat_mode_support to compat_mode_supported

> +
> +static int compat_mode_detect(void)
> +{
> +	unsigned long tmp = csr_read(CSR_STATUS);
> +
> +	csr_write(CSR_STATUS, (tmp & ~SR_UXL) | SR_UXL_32);
> +
> +	if ((csr_read(CSR_STATUS) & SR_UXL) != SR_UXL_32) {
> +		pr_info("riscv: 32bit compat mode detect failed\n");
> +		compat_mode_support = false;
> +	} else {
> +		compat_mode_support = true;
> +		pr_info("riscv: 32bit compat mode detected\n");
> +	}

I don't think we need these printks here.

Also this could be simplified to:

	compat_mode_supported = (csr_read(CSR_STATUS) & SR_UXL) == SR_UXL_32;
Guo Ren Feb. 3, 2022, 2:44 a.m. UTC | #3 
On Wed, Feb 2, 2022 at 3:52 PM Christoph Hellwig <hch@lst.de> wrote:
>
> On Tue, Feb 01, 2022 at 11:05:39PM +0800, guoren@kernel.org wrote:
> > +bool compat_elf_check_arch(Elf32_Ehdr *hdr)
> > +{
> > +     if (compat_mode_support && (hdr->e_machine == EM_RISCV))
> > +             return true;
> > +     else
> > +             return false;
> > +}
>
> This can be simplified to:
>
>         return compat_mode_support && hdr->e_machine == EM_RISCV;
Good point.

>
> I'd also rename compat_mode_support to compat_mode_supported
Okay

>
> > +
> > +static int compat_mode_detect(void)
> > +{
> > +     unsigned long tmp = csr_read(CSR_STATUS);
> > +
> > +     csr_write(CSR_STATUS, (tmp & ~SR_UXL) | SR_UXL_32);
> > +
> > +     if ((csr_read(CSR_STATUS) & SR_UXL) != SR_UXL_32) {
> > +             pr_info("riscv: 32bit compat mode detect failed\n");
> > +             compat_mode_support = false;
> > +     } else {
> > +             compat_mode_support = true;
> > +             pr_info("riscv: 32bit compat mode detected\n");
> > +     }
>
> I don't think we need these printks here.
Okay

>
> Also this could be simplified to:
>
>         compat_mode_supported = (csr_read(CSR_STATUS) & SR_UXL) == SR_UXL_32;
Okay
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h
index aee40040917b..3a4293dc7229 100644
--- a/arch/riscv/include/asm/elf.h
+++ b/arch/riscv/include/asm/elf.h
@@ -40,7 +40,8 @@ 
  * elf64_hdr e_machine's offset are different. The checker is
  * a little bit simple compare to other architectures.
  */
-#define compat_elf_check_arch(x) ((x)->e_machine == EM_RISCV)
+extern bool compat_elf_check_arch(Elf32_Ehdr *hdr);
+#define compat_elf_check_arch	compat_elf_check_arch
 
 #define CORE_DUMP_USE_REGSET
 #define ELF_EXEC_PAGESIZE	(PAGE_SIZE)
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 1a666ad299b4..758847cba391 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -83,6 +83,38 @@  void show_regs(struct pt_regs *regs)
 		dump_backtrace(regs, NULL, KERN_DEFAULT);
 }
 
+#ifdef CONFIG_COMPAT
+static bool compat_mode_support __read_mostly;
+
+bool compat_elf_check_arch(Elf32_Ehdr *hdr)
+{
+	if (compat_mode_support && (hdr->e_machine == EM_RISCV))
+		return true;
+	else
+		return false;
+}
+
+static int compat_mode_detect(void)
+{
+	unsigned long tmp = csr_read(CSR_STATUS);
+
+	csr_write(CSR_STATUS, (tmp & ~SR_UXL) | SR_UXL_32);
+
+	if ((csr_read(CSR_STATUS) & SR_UXL) != SR_UXL_32) {
+		pr_info("riscv: 32bit compat mode detect failed\n");
+		compat_mode_support = false;
+	} else {
+		compat_mode_support = true;
+		pr_info("riscv: 32bit compat mode detected\n");
+	}
+
+	csr_write(CSR_STATUS, tmp);
+
+	return 0;
+}
+arch_initcall(compat_mode_detect);
+#endif
+
 void start_thread(struct pt_regs *regs, unsigned long pc,
 	unsigned long sp)
 {