From patchwork Sun Feb 20 05:08:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12752552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2722C433F5 for ; Sun, 20 Feb 2022 05:10:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RXrj96bkTaxm5t0XPpm5QU2QV7i52UNWUFtA3t2MxkE=; b=ZLJDt/28RrADnY gpgIAcxiqCQ3rU3XS+UydNvSdCdNm4BlcCaiApfhx7Y3c9DvToetk2OST5MEZwO8ycVHjKQfn/PW6 qLTlb5ZFY6TgyiGTun4vcCrhhOZWsynLaSx5YaqSq9I2CWGGsDYSXU+K6gWNMuOylf36Ajyrk/iXK 1zPHEySsBIwuKthJWreoiM/UEig3lE8R0ucE6bI8Vqqk5ChVMF8eaPvh07VjQmyOfleGwxDAh2lYZ kDDiHejw7/nuDLknTu9qMOfqYvdWSbIJ67tTaC8lLEKcpAYMUq3C50aQ1p9cbPuN7JDIxG/MRMtbe L2alhotYAW4d4N6Vymgw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLeUC-000c1j-BJ; Sun, 20 Feb 2022 05:10:16 +0000 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nLeU9-000bzy-Lf for linux-riscv@lists.infradead.org; Sun, 20 Feb 2022 05:10:15 +0000 Received: by mail-pj1-x102f.google.com with SMTP id y16so3863406pjt.0 for ; Sat, 19 Feb 2022 21:10:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kq1GecPvvHHYiTo+a1VD34ISckL9lL5R+wkUykUsBYs=; b=ILLVLdm5mDr5L3R2lCPOyklnyboP1+NYbCs97ijrIlRwfb9xtODA915qMQpH5sVhld 2ja4WxPCNsPdiZkDdcQhYpLOujMv+y62OhvlW/CnxNjkylf5Ec/ssEmvGntYOeqaSspc QpJPfkyJsthuCklgUCzXvBIR4BGHogNM7Tt7ibMCQ+SpshV3VuK/RCwo3thQtjZtoKf4 kP8dOYl9laA+Y4d8E5FMe0yy2BYOjs3DqCRxo8HZ1r12ogMRAG919HHLVDORLDYVndxL mSQNUnQ+Zpl5GiG42OCmj5+DgdwD3cAmVz9J0a0hRIoA5AnKX8EQ+UbmCwpvgBliXzkx +dWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kq1GecPvvHHYiTo+a1VD34ISckL9lL5R+wkUykUsBYs=; b=ZfBOm02SVSUz+7U/Tey48CkFS1QFkxW0WdR8Yd+Q342maB/CUFzN+LUQwNki9XQUhO K672Ng9e4wYvEvRUc72B5B821Qn2VsxQjzUfP5S59+n/eyvwj7tlwW2130/+yXc5WJxw Fl2kswD4fMrgGbcQacnMMQn7wsoNctWq3AkBvR/OU03SSy+C7fcBKcLsPwvXLe3oHguC 3zg0oTQOvsNCOuT3h8DUhKql4MSnnHHzMqa1jVKTsF+Fq2VQ6/mF8H2mwmt8ZZ7w2srQ bEvYNlfBbk1N7mIix4XIGv0a/O5WffsO4ZcrYFduCg8MHg3o1APzy1n7UUJIRPkrB+bo gHRA== X-Gm-Message-State: AOAM532XqvubTI2TJ4qrAjgZ8bs5H+4vbGj5YGYCFHVjztGdDsvE9k1R k2QiUd38fTLSZlaJn+4D/2B9GQ== X-Google-Smtp-Source: ABdhPJyZEgyeiIBog+nZvfXsy+MKFhYfDCXuTo/yIMPtvH3hboXy2T7+AYuPdek62bU4y8SzV2VAoA== X-Received: by 2002:a17:902:834a:b0:14f:3337:35de with SMTP id z10-20020a170902834a00b0014f333735demr14471866pln.8.1645333812882; Sat, 19 Feb 2022 21:10:12 -0800 (PST) Received: from localhost.localdomain ([122.162.118.38]) by smtp.gmail.com with ESMTPSA id 84sm7602730pfx.181.2022.02.19.21.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Feb 2022 21:10:12 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 4/6] RISC-V: Allow marking IPIs as suitable for remote FENCEs Date: Sun, 20 Feb 2022 10:38:52 +0530 Message-Id: <20220220050854.743420-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220220050854.743420-1-apatel@ventanamicro.com> References: <20220220050854.743420-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220219_211013_743405_4AAE8C09 X-CRM114-Status: GOOD ( 18.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the RISC-V kernel instead of using SBI calls. The upcoming ACLINT [M|S]SWI devices and AIA IMSIC devices allow direct IPI injection from the RISC-V kernel. To support this, we extend the riscv_ipi_set_virq_range() function so that irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel --- arch/riscv/include/asm/ipi-mux.h | 2 ++ arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/ipi-mux.c | 3 ++- arch/riscv/kernel/sbi.c | 3 ++- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 6 files changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/ipi-mux.h b/arch/riscv/include/asm/ipi-mux.h index 988e2bba372a..3a5acbf51806 100644 --- a/arch/riscv/include/asm/ipi-mux.h +++ b/arch/riscv/include/asm/ipi-mux.h @@ -15,6 +15,7 @@ void riscv_ipi_mux_handle_irq(void); /* Create irq_domain for muxed IPIs */ struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)); @@ -28,6 +29,7 @@ static inline void riscv_ipi_mux_handle_irq(void) } static inline struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 178fe4ada592..ddd3be1c77b6 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr_irqs); +void riscv_ipi_set_virq_range(int virq, int nr_irqs, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -93,10 +101,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/ipi-mux.c b/arch/riscv/kernel/ipi-mux.c index 3a0405f0e0de..544074ea3ead 100644 --- a/arch/riscv/kernel/ipi-mux.c +++ b/arch/riscv/kernel/ipi-mux.c @@ -144,6 +144,7 @@ static int ipi_mux_starting_cpu(unsigned int cpu) } struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, + bool use_for_rfence, void (*clear_ipi)(void), void (*send_ipi)(const struct cpumask *mask)) { @@ -198,7 +199,7 @@ struct irq_domain *riscv_ipi_mux_create(bool use_soft_irq, "irqchip/riscv/ipi-mux:starting", ipi_mux_starting_cpu, ipi_mux_dying_cpu); - riscv_ipi_set_virq_range(virq, BITS_PER_LONG); + riscv_ipi_set_virq_range(virq, BITS_PER_LONG, use_for_rfence); return ipi_mux_priv.domain; diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index fa3d92fce9f8..210d23524771 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -630,7 +630,8 @@ static void sbi_ipi_clear(void) void __init sbi_ipi_init(void) { - if (riscv_ipi_mux_create(true, sbi_ipi_clear, sbi_send_cpumask_ipi)) + if (riscv_ipi_mux_create(true, false, + sbi_ipi_clear, sbi_send_cpumask_ipi)) pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index a9f1aca38358..b98d9c319f6f 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -149,7 +149,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; @@ -172,6 +175,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index b05a9e946633..607d47dab896 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -224,7 +224,7 @@ static int __init clint_timer_init_dt(struct device_node *np) goto fail_free_irq; } - riscv_ipi_mux_create(true, clint_clear_ipi, clint_send_ipi); + riscv_ipi_mux_create(true, true, clint_clear_ipi, clint_send_ipi); clint_clear_ipi(); return 0;