| Message ID | 20220308132806.96095-1-Niklas.Cassel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] riscv: dts: canaan: Fix SPI3 bus width | expand |
On 3/8/22 22:28, Niklas Cassel wrote: > From: Niklas Cassel <niklas.cassel@wdc.com> > > According to the K210 Standalone SDK Programming guide: > https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf > > Section 15.4.3.3: > SPI0 and SPI1 supports: standard, dual, quad and octal transfers. > SPI3 supports: standard, dual and quad transfers (octal is not supported). > > In order to support quad transfers (Quad SPI), SPI3 must have four IO wires > connected to the SPI flash. > > Update the device tree to specify the correct bus width. > > Tested on maix bit, maix dock and maixduino, which all have the same > SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it > would not make sense for this k210 board to be designed differently. > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Looks OK to me. Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> > --- > Changes since v1: > -Add the new properties directly after spi-max-frequency for all DT board > files. > > arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 ++ > arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 ++ > arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 ++ > arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 ++ > 4 files changed, 8 insertions(+) > > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > index 984872f3d3a9..b9e30df127fe 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > @@ -203,6 +203,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts > index 7ba99b4da304..8d23401b0bbb 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts > @@ -205,6 +205,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts > index be9b12c9b374..24fd83b43d9d 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts > @@ -213,6 +213,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts > index 031c0c28f819..25341f38292a 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts > @@ -178,6 +178,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > };
On Tue, Mar 08, 2022 at 02:28:05PM +0100, Niklas Cassel wrote: > From: Niklas Cassel <niklas.cassel@wdc.com> > > According to the K210 Standalone SDK Programming guide: > https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf > > Section 15.4.3.3: > SPI0 and SPI1 supports: standard, dual, quad and octal transfers. > SPI3 supports: standard, dual and quad transfers (octal is not supported). > > In order to support quad transfers (Quad SPI), SPI3 must have four IO wires > connected to the SPI flash. > > Update the device tree to specify the correct bus width. > > Tested on maix bit, maix dock and maixduino, which all have the same > SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it > would not make sense for this k210 board to be designed differently. > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > --- Hello Palmer, any chance of this getting picked up? Kind regards, Niklas
On Tue, 08 Mar 2022 05:28:05 PST (-0800), Niklas.Cassel@wdc.com wrote: > From: Niklas Cassel <niklas.cassel@wdc.com> > > According to the K210 Standalone SDK Programming guide: > https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf > > Section 15.4.3.3: > SPI0 and SPI1 supports: standard, dual, quad and octal transfers. > SPI3 supports: standard, dual and quad transfers (octal is not supported). > > In order to support quad transfers (Quad SPI), SPI3 must have four IO wires > connected to the SPI flash. > > Update the device tree to specify the correct bus width. > > Tested on maix bit, maix dock and maixduino, which all have the same > SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it > would not make sense for this k210 board to be designed differently. > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > --- > Changes since v1: > -Add the new properties directly after spi-max-frequency for all DT board > files. > > arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 ++ > arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 ++ > arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 ++ > arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 ++ > 4 files changed, 8 insertions(+) > > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > index 984872f3d3a9..b9e30df127fe 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > @@ -203,6 +203,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts > index 7ba99b4da304..8d23401b0bbb 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts > @@ -205,6 +205,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts > index be9b12c9b374..24fd83b43d9d 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts > @@ -213,6 +213,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; > diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts > index 031c0c28f819..25341f38292a 100644 > --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts > @@ -178,6 +178,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; Thanks, this is on for-next.
Hi Niklas, On Tue, Mar 8, 2022 at 2:30 PM Niklas Cassel <Niklas.Cassel@wdc.com> wrote: > From: Niklas Cassel <niklas.cassel@wdc.com> > According to the K210 Standalone SDK Programming guide: > https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf > > Section 15.4.3.3: > SPI0 and SPI1 supports: standard, dual, quad and octal transfers. > SPI3 supports: standard, dual and quad transfers (octal is not supported). > > In order to support quad transfers (Quad SPI), SPI3 must have four IO wires > connected to the SPI flash. > > Update the device tree to specify the correct bus width. > > Tested on maix bit, maix dock and maixduino, which all have the same > SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it > would not make sense for this k210 board to be designed differently. > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > --- > Changes since v1: > -Add the new properties directly after spi-max-frequency for all DT board > files. Thanks for your patch, which is now commit 6846d656106add3a ("riscv: dts: canaan: Fix SPI3 bus width") in v5.18-rc1. > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > @@ -203,6 +203,8 @@ flash@0 { > compatible = "jedec,spi-nor"; > reg = <0>; > spi-max-frequency = <50000000>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > m25p,fast-read; > broken-flash-reset; > }; On MAiX BiT, I get: +spi spi1.0: setup: ignoring unsupported mode bits a00 spi-nor spi1.0: gd25lq128d (16384 Kbytes) Perhaps this depends on a not-yet-applied patch to add quad support to the SPI driver? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Tue, Apr 05, 2022 at 02:26:53PM +0200, Geert Uytterhoeven wrote: > Hi Niklas, > > On Tue, Mar 8, 2022 at 2:30 PM Niklas Cassel <Niklas.Cassel@wdc.com> wrote: > > From: Niklas Cassel <niklas.cassel@wdc.com> > > According to the K210 Standalone SDK Programming guide: > > https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf > > > > Section 15.4.3.3: > > SPI0 and SPI1 supports: standard, dual, quad and octal transfers. > > SPI3 supports: standard, dual and quad transfers (octal is not supported). > > > > In order to support quad transfers (Quad SPI), SPI3 must have four IO wires > > connected to the SPI flash. > > > > Update the device tree to specify the correct bus width. > > > > Tested on maix bit, maix dock and maixduino, which all have the same > > SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it > > would not make sense for this k210 board to be designed differently. > > > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > > --- > > Changes since v1: > > -Add the new properties directly after spi-max-frequency for all DT board > > files. > > Thanks for your patch, which is now commit 6846d656106add3a ("riscv: > dts: canaan: Fix SPI3 bus width") in v5.18-rc1. > > > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > > @@ -203,6 +203,8 @@ flash@0 { > > compatible = "jedec,spi-nor"; > > reg = <0>; > > spi-max-frequency = <50000000>; > > + spi-tx-bus-width = <4>; > > + spi-rx-bus-width = <4>; > > m25p,fast-read; > > broken-flash-reset; > > }; > > On MAiX BiT, I get: > > +spi spi1.0: setup: ignoring unsupported mode bits a00 > spi-nor spi1.0: gd25lq128d (16384 Kbytes) Hello Geert, The device tree is supposed to describe the hardware. The Synopsys SPI controller and the Gigadevice SPI flash both support quad transfers. It would be incorrect to adapt the device tree based on current limitations of the drivers/spi/spi-dw-core.c driver. Likewise, we shouldn't need to update the device tree if the dwc driver ever adds support for quad transfers. However, I do agree that it is a bit weird that the kernel outputs a warning for this case. I understand that the warning is supposed to be there to warn that a controller does not support a mode required by the driver, but if it is the driver and not the controller that lacks support, is a warning really warranted? I'm not so sure. Adding Mark Brown to hopefully hear his opinion. Kind regards, Niklas
Hi Niklas, On Tue, Apr 5, 2022 at 3:03 PM Niklas Cassel <Niklas.Cassel@wdc.com> wrote: > On Tue, Apr 05, 2022 at 02:26:53PM +0200, Geert Uytterhoeven wrote: > > On Tue, Mar 8, 2022 at 2:30 PM Niklas Cassel <Niklas.Cassel@wdc.com> wrote: > > > From: Niklas Cassel <niklas.cassel@wdc.com> > > > According to the K210 Standalone SDK Programming guide: > > > https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf > > > > > > Section 15.4.3.3: > > > SPI0 and SPI1 supports: standard, dual, quad and octal transfers. > > > SPI3 supports: standard, dual and quad transfers (octal is not supported). > > > > > > In order to support quad transfers (Quad SPI), SPI3 must have four IO wires > > > connected to the SPI flash. > > > > > > Update the device tree to specify the correct bus width. > > > > > > Tested on maix bit, maix dock and maixduino, which all have the same > > > SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it > > > would not make sense for this k210 board to be designed differently. > > > > > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > > > --- > > > Changes since v1: > > > -Add the new properties directly after spi-max-frequency for all DT board > > > files. > > > > Thanks for your patch, which is now commit 6846d656106add3a ("riscv: > > dts: canaan: Fix SPI3 bus width") in v5.18-rc1. > > > > > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > > > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > > > @@ -203,6 +203,8 @@ flash@0 { > > > compatible = "jedec,spi-nor"; > > > reg = <0>; > > > spi-max-frequency = <50000000>; > > > + spi-tx-bus-width = <4>; > > > + spi-rx-bus-width = <4>; > > > m25p,fast-read; > > > broken-flash-reset; > > > }; > > > > On MAiX BiT, I get: > > > > +spi spi1.0: setup: ignoring unsupported mode bits a00 > > spi-nor spi1.0: gd25lq128d (16384 Kbytes) > > The device tree is supposed to describe the hardware. > > The Synopsys SPI controller and the Gigadevice SPI flash both support quad > transfers. > > It would be incorrect to adapt the device tree based on current limitations > of the drivers/spi/spi-dw-core.c driver. > > Likewise, we shouldn't need to update the device tree if the dwc driver > ever adds support for quad transfers. I fully agree with that. I was just wondering whether work is underway to add quad support to the SPI controller driver. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Tue, Apr 05, 2022 at 03:09:35PM +0200, Geert Uytterhoeven wrote: > Hi Niklas, > > On Tue, Apr 5, 2022 at 3:03 PM Niklas Cassel <Niklas.Cassel@wdc.com> wrote: > > On Tue, Apr 05, 2022 at 02:26:53PM +0200, Geert Uytterhoeven wrote: > > > On Tue, Mar 8, 2022 at 2:30 PM Niklas Cassel <Niklas.Cassel@wdc.com> wrote: > > > > From: Niklas Cassel <niklas.cassel@wdc.com> > > > > According to the K210 Standalone SDK Programming guide: > > > > https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf > > > > > > > > Section 15.4.3.3: > > > > SPI0 and SPI1 supports: standard, dual, quad and octal transfers. > > > > SPI3 supports: standard, dual and quad transfers (octal is not supported). > > > > > > > > In order to support quad transfers (Quad SPI), SPI3 must have four IO wires > > > > connected to the SPI flash. > > > > > > > > Update the device tree to specify the correct bus width. > > > > > > > > Tested on maix bit, maix dock and maixduino, which all have the same > > > > SPI flash (gd25lq128d) connected to SPI3. maix go is untested, but it > > > > would not make sense for this k210 board to be designed differently. > > > > > > > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > > > > --- > > > > Changes since v1: > > > > -Add the new properties directly after spi-max-frequency for all DT board > > > > files. > > > > > > Thanks for your patch, which is now commit 6846d656106add3a ("riscv: > > > dts: canaan: Fix SPI3 bus width") in v5.18-rc1. > > > > > > > --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > > > > +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts > > > > @@ -203,6 +203,8 @@ flash@0 { > > > > compatible = "jedec,spi-nor"; > > > > reg = <0>; > > > > spi-max-frequency = <50000000>; > > > > + spi-tx-bus-width = <4>; > > > > + spi-rx-bus-width = <4>; > > > > m25p,fast-read; > > > > broken-flash-reset; > > > > }; > > > > > > On MAiX BiT, I get: > > > > > > +spi spi1.0: setup: ignoring unsupported mode bits a00 > > > spi-nor spi1.0: gd25lq128d (16384 Kbytes) > > > > The device tree is supposed to describe the hardware. > > > > The Synopsys SPI controller and the Gigadevice SPI flash both support quad > > transfers. > > > > It would be incorrect to adapt the device tree based on current limitations > > of the drivers/spi/spi-dw-core.c driver. > > > > Likewise, we shouldn't need to update the device tree if the dwc driver > > ever adds support for quad transfers. > > I fully agree with that. > > I was just wondering whether work is underway to add quad support > to the SPI controller driver. Hello Geert, Not planned from my side :( I'm actually quite surprised that the dwc driver doesn't support it yet, considering how popular this IP is, and considering that a lot for SPI drivers (for other SPI controllers) support it already. FWIW, neither nommu_k210_defconfig nor nommu_k210_sdcard_defconfig have CONFIG_MTD_SPI_NOR set, so at least the only people who will see the warning is people who are explicitly enabling support for the SPI flash. Kind regards, Niklas
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts index 984872f3d3a9..b9e30df127fe 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts @@ -203,6 +203,8 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; broken-flash-reset; }; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts index 7ba99b4da304..8d23401b0bbb 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -205,6 +205,8 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; broken-flash-reset; }; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts index be9b12c9b374..24fd83b43d9d 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts @@ -213,6 +213,8 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; broken-flash-reset; }; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts index 031c0c28f819..25341f38292a 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -178,6 +178,8 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; broken-flash-reset; };