From patchwork Fri Apr 8 14:36:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12806854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7EE3C433EF for ; Fri, 8 Apr 2022 14:38:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5VRaBiNRwicaiASp0f3rmpsC/jFFnWHXmayMQfxG8as=; b=Ix07qrScuiFZWW uQXQq13daLGK/ZpYhi78EZUIihPOUw+vEHUfEPqOOQGPer7pE97YmBF3UA230Yms9Afkl/csfWjSp wG3cmH7MNSXfOLAMP5hdKuVAZG0gVH5+b8+0fL6U/56XK06kpUU2hXLgezj/CY9n72eBKnz+sOkEM F3JTNzEn5JzyseqjeNNlEhM0HkcoTcn+LFo/2KKvMptzYKMblidpxErkS2rs0a0jnVKqXT685xHdD cFXOiOZz0OS0GXp9v4VQtoRWUYY4nYEVALXIhmIh4Fn5WCanSdxldxRc+QidBWaBRpmbNaVBzPRwq Z+479R2NC0WPKAVF05LQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkd-0000rY-3M; Fri, 08 Apr 2022 14:38:15 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ncpkN-0000dE-St for linux-riscv@lists.infradead.org; Fri, 08 Apr 2022 14:38:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649428679; x=1680964679; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ooZZ+ZTqJwMh290JL9lbt0QfWALbJVpmgRpSeNwWcbk=; b=wREYQ8cX6FtapKKKmZHOytYHZzWUouGk6Bp1bTnOHpwM8T1HCNkVZhaA ACUDKL0NjkfBS2kveud5LQjXHl7GbNNxWqAKjiFjM841hvm8yobLsgRub mZwtZnfKDttt6fd+P9dj62r4FFGtp/U9fhZb2Gz6XCUfSi9wYNgruImvz El0P7oc4Psdnj+lV8nu1a6paSbK1oNJI7gnXYl4r0TvZocMTxtiZdCNJG no4L1z9O5PMCB8KkirVwPuDoEIRVn11JMgD/GQiFXhoOPSkygCEueuSJd StdEqyXPgJL0ynIGcrMvKftvwsPqUKJhOZaeKqUMzL+YMjHLQOM/+JwdQ g==; X-IronPort-AV: E=Sophos;i="5.90,245,1643698800"; d="scan'208";a="154925662" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 07:37:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 07:37:59 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 07:37:56 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 5/7] clk: microchip: mpfs: rename sys_base to base Date: Fri, 8 Apr 2022 14:36:45 +0000 Message-ID: <20220408143646.3693104-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_073800_052252_D9417194 X-CRM114-Status: GOOD ( 12.11 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Having added a second set of registers for the msspll, sys_base no longer really makes sense as a variable name. Renaming it to base will make it consistent with mpfs_clock_data & several function arguments. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 66251a5f4a03..f22d4b40ef28 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -55,7 +55,7 @@ struct mpfs_cfg_clock { struct mpfs_cfg_hw_clock { struct mpfs_cfg_clock cfg; - void __iomem *sys_base; + void __iomem *base; struct clk_hw hw; struct clk_init_data init; }; @@ -69,7 +69,7 @@ struct mpfs_periph_clock { struct mpfs_periph_hw_clock { struct mpfs_periph_clock periph; - void __iomem *sys_base; + void __iomem *base; struct clk_hw hw; }; @@ -168,7 +168,7 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; + void __iomem *base_addr = cfg_hw->base; u32 val; val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; @@ -189,7 +189,7 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned { struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; + void __iomem *base_addr = cfg_hw->base; unsigned long flags; u32 val; int divider_setting; @@ -236,9 +236,9 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { }; static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, - void __iomem *sys_base) + void __iomem *base) { - cfg_hw->sys_base = sys_base; + cfg_hw->base = base; return devm_clk_hw_register(dev, &cfg_hw->hw); } @@ -246,14 +246,14 @@ static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *c static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; + void __iomem *base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; - ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); + ret = mpfs_clk_register_cfg(dev, cfg_hw, base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", cfg_hw->cfg.id); @@ -273,7 +273,7 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; + void __iomem *base_addr = periph_hw->base; u32 reg, val; unsigned long flags; @@ -292,7 +292,7 @@ static void mpfs_periph_clk_disable(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; + void __iomem *base_addr = periph_hw->base; u32 reg, val; unsigned long flags; @@ -309,7 +309,7 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) { struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; + void __iomem *base_addr = periph_hw->base; u32 reg; reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); @@ -379,9 +379,9 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { }; static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, - void __iomem *sys_base) + void __iomem *base) { - periph_hw->sys_base = sys_base; + periph_hw->base = base; return devm_clk_hw_register(dev, &periph_hw->hw); } @@ -389,14 +389,14 @@ static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_cl static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; + void __iomem *base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; - ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); + ret = mpfs_clk_register_periph(dev, periph_hw, base); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", periph_hw->periph.id);