From patchwork Wed May 11 21:41:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 12846631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 509CDC433EF for ; Wed, 11 May 2022 21:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=miSWrYMBY0fblCfI7nDTaIysLCYWpfkBODeDNS42rIg=; b=GOh3jHnkvdlmPJ B/Gi3UDKu8kKU207D3AaZNqnC0uEoraivBI1JSj6LJycrN4EHcsOdMQYzb/ErnVEXWliHuvbnbW6v n0sUFXICDoqktu6ajsONtDgTYxyOZBUcHv+dR8B9JRqi9uH36syQxgdKoJmQHFqDD8n4XeERRA+mc AaGWrz0sXq7TDbmMKiBLUVdhXax9amUBH5Jm4cbtmWAiU7NJcy5otqaCfi1SBI6FFLbIU9nZD6iAn zP2n3EbuhPukSvb7omjwlHPiqvWUENVb1NsP7Fx+XKEI8bxGLGbDnzlDG4TqW04CulWqr/DGM/om7 EXg98B64fRL6Ap10kzDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nou5T-008p4s-4s; Wed, 11 May 2022 21:41:39 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nou5Q-008p36-77 for linux-riscv@lists.infradead.org; Wed, 11 May 2022 21:41:37 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nou5O-0005NU-Ka; Wed, 11 May 2022 23:41:34 +0200 From: Heiko Stuebner To: palmer@dabbelt.com, paul.walmsley@sifive.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size Date: Wed, 11 May 2022 23:41:30 +0200 Message-Id: <20220511214132.2281431-2-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220511214132.2281431-1-heiko@sntech.de> References: <20220511214132.2281431-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220511_144136_289489_97BD44FD X-CRM114-Status: UNSURE ( 9.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Zicbom operates on a block-size defined for the cpu-core, which does not necessarily match other cache-sizes used. So add the necessary property for the system to know the core's block-size. Signed-off-by: Heiko Stuebner Reviewed-by: Anup Patel --- Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..b179bfd155a3 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -63,6 +63,13 @@ properties: - riscv,sv48 - riscv,none + riscv,cbom-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Blocksize in bytes for the Zicbom cache operations. The block + size is a property of the core itself and does not necessarily + match other software defined cache sizes. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture